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Superconductor Science and Technology

Design guidelines for Suzuki stacks as reliable high-speed Josephson voltage drivers

Thomas Ortlepp, L Zheng, Stephen R. Whiteley, T. Van Duzer

Published Jan 21, 2013• 25 citations
Publisher

Abstract

The application of superconducting circuits for high-performance computing and high-speed analog-to-digital converters suffers from the difficulty of amplifying the weak signals of superconducting circuits to the volt level of semiconductor electronics. We refer to the most accepted Josephson circuit used to amplify weak signals of about a millivolt to several tens of millivolts as a Suzuki stack. It can be directly triggered by a single flux quantum pulse and has a very high switching speed of about 25 ps. We report here an in-depth study of design issues for Suzuki stacks with extensive systematic simulations as well as experimental results. We explain the origin of previously reported phenomena such as multiple-level switching, high bit-error-rates, and interactions between stacks, and give design guidance for avoidance of such problems. We show experimental results for a set of Suzuki stacks operating correctly and independently with a single power supply. The presented design guidelines address important characteristics that need to be optimized: output voltage, bias margins, operating frequency, bit-error-rate, delay, power dissipation, and physical size.

DOI
10.1088/0953-2048/26/3/035007

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The application of superconducting circuits for high-performance computing and high-speed analog-to-digital converters suffers from the difficulty of amplifying the weak signals of superconducting circuits to the volt level of semiconductor electronics. We refer to the most accepted Josephson circuit used to amplify weak signals of about a millivolt to several tens of millivolts as a Suzuki stack. It can be directly triggered by a single flux quantum pulse and has a very high switching speed of about 25 ps. We report here an in-depth study of design issues for Suzuki stacks with extensive systematic simulations as well as experimental results. We explain the origin of previously reported phenomena such as multiple-level switching, high bit-error-rates, and interactions between stacks, and give design guidance for avoidance of such problems. We show experimental results for a set of Suzuki stacks operating correctly and independently with a single power supply. The presented design guidelines address important characteristics that need to be optimized: output voltage, bias margins, operating frequency, bit-error-rate, delay, power dissipation, and physical size.
Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least$\pm$20% of process parameter variations as demonstrated with extensive simulations.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
Abstract Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables.
Suzuki stack circuits, a type of latching high-voltage driver circuit, are widely used in Josephson–CMOS hybrid memories. The existing Suzuki stack designs utilize only single-ended signaling when connected to a CMOS amplifier. In this article, a Suzuki stack circuit with a differential output is proposed by producing both the positive and negative output voltages. The negative output voltage is produced by using a negative biasing network and a negative single-flux quantum (SFQ) input pulse, which is generated by the proposed positive-to-negative SFQ converter. As compared to a conventional single-ended Suzuki stack circuit, the proposed differential design can provide two times higher output voltage swing and better immunity to noise without degrading the operating margins. Potential advantages and drawbacks of the proposed circuit are explored in this article.
We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.