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IEEE International Symposium on Circuits and Systems proceedings

Modified shuffled schedule for nonbinary low-density parity-check codes

Jun Ting Lin, Zhiyuan Yan

Published May 1, 2012• 0 citations
Publisher

Abstract

In this paper, a shuffled schedule of the Min-Max decoding algorithm is proposed for nonbinary LDPC codes. To reduce the latency and memory requirement, a modified shuffled schedule with much simpler check node processing is also proposed, based on a new shuffle sort algorithm. Numerical simulations for three LDPC codes over GF(32) with different lengths and rates show: (1) both the shuffled and modified shuffled schedule converge faster and have slightly better error performance than the flooding schedule, and (2) the degradation of the modified shuffled schedule in error performance as well as convergence rate is negligible.

DOI
10.1109/iscas.2012.6271606

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In this paper, a shuffled schedule of the Min-Max decoding algorithm is proposed for nonbinary LDPC codes. To reduce the latency and memory requirement, a modified shuffled schedule with much simpler check node processing is also proposed, based on a new shuffle sort algorithm. Numerical simulations for three LDPC codes over GF(32) with different lengths and rates show: (1) both the shuffled and modified shuffled schedule converge faster and have slightly better error performance than the flooding schedule, and (2) the degradation of the modified shuffled schedule in error performance as well as convergence rate is negligible.
In this brief, a shuffled schedule (SS) of the min-max decoding algorithm is proposed for nonbinary low-density parity-check (LDPC) codes. To increase the throughput and reduce the memory requirement, a modified SS (MSS) with much simpler check node processing is also proposed, based on a new shuffled merge algorithm. Numerical simulations for three LDPC codes with different lengths and rates over GF(32) show: 1) both SS and MSS converge faster and have slightly better error performance than the flooding schedule, and 2) the degradation of the MSS in error performance as well as convergence rate is negligible. Finally, an efficient decoder architecture based on the MSS is proposed for quasi-cyclic LDPC codes. The proposed decoder architecture further enhances the decoding throughput with improved check and variable node processing units. The implementation results of an (837, 726) LDPC decoder over GF(32) demonstrate that the proposed architecture outperforms those in previous works.
Low-density parity-check (LDPC) codes have proved to be very powerful channel coding schemes with a broad range of applications. However, as maximum-likelihood decoding is utterly complex, suboptimal decoders have to be employed. One of the most popular decoding algorithms of LDPC codes is belief propagation (BP) decoding. In this paper, we present a novel scheduling for belief propagation decoding of LDPC codes. The new approach combines probabilistic scheduling with the known shuffled and check-shuffled serial scheduling algorithms. The resulting probabilistic shuffled and probabilistic check-shuffled decoders show a superior performance in terms of residual bit error rate. The drawback is that the convergence speed is slightly decreased. However, the convergence is still faster than for the standard and probabilistic flooding algorithms. Furthermore, we have adapted the probabilistic flooding schedule and the proposed probabilistic shuffled schedule to the non-binary case. We show that the aforementioned effects on the binary decoder can similarly be observed when applying the different schedules to the decoding of LDPC codes over higher order Galois fields.
When the code length is moderate, non-binary low-density parity-check (NB-LDPC) codes can achieve better error correcting performance than their binary counterparts at the expense of higher decoding complexity. The check node processing is a major bottleneck of NB-LDPC decoding. In this paper, Min-max decoding algorithm is proposed based on a new forward backward processing method of check nodes, select only a part of the most reliable information to the forward-backward calculation process, and change the variable nodes to check nodes (v-to-c) generation of information. Using this algorithm, a kind of code (768,1152) defined on GF(4) is simulated and compared with belief propagation in log domain (LOG-BP) decoding algorithm. Simulation results show Min-max decoding algorithm reduce information storage requirements and the computational complexity, conducive to engineering implementation.
Compared to binary low-density parity-check (LDPC) codes, non-binary (NB) LDPC codes can achieve higher coding gain when the code length is moderate. On the other hand, the decoding of NB-LDPC codes is more complicated since a vector of messages instead of a single message is passed along each edge of the associated Tanner graph. Layered decoding can be employed to simplify LDPC decoding. However, there is extra latency between the decoding of layers caused by check node processing, message permutation and updating when applied to NB-LDPC codes. In this paper, a novel scheduling scheme is developed to eliminate the extra latency for the Min-max decoding of quasi-cyclic (QC) NB-LDPC codes using trellis-based check node processing. Assume that each row of sub-matrices in the parity check matrix of a QCNB-LDPC code is divided into two layers, the proposed scheme can reduce the decoding latency by a factor of around (2dc+ 5)/2dc, where dcis the check node degree. It leads to significant speedup when dcis not large. Moreover, the area overhead of the proposed scheme is less than 10%.
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance.Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency.In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed.Compare with previous works, less than 52% could be reduced for the latency of check node unit.In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NB-QC-LDPC decoder.
Recently low-density parity check (LDPC) codes have been applied in more areas, and the research of non-binary LDPC codes has become more significant. In this paper, we establish a dynamic scheduling strategy to reduce complexity of non-binary LDPC codes decoding, and choose extended min-sum algorithm as the model. The dynamic scheduling strategy is based on the idea of nodes reliability. When decoding, we select a part of check nodes to update messages in real time according to the reliability rules, and only the variable nodes getting new messages can participate in the message propagation. Compared with usual standard flooding scheduling, this dynamic scheduling strategy can reduce decoding complexity effectively. We also optimize the message of variable nodes according to reliability, which ensure that the error correction performance of decoding algorithm is not affected. Our simulations over a BPSK-AWGN channel show that this dynamic scheduling strategy can reduce complexity in non-binary LDPC codes belief propagation decoding without affecting error correction performance.