IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Reduced-latency scheduling scheme for min-max non-binary LDPC decoding

Xinmiao Zhang, Fang Cai

Published Dec 1, 2010• 4 citations

Abstract

Compared to binary low-density parity-check (LDPC) codes, non-binary (NB) LDPC codes can achieve higher coding gain when the code length is moderate. On the other hand, the decoding of NB-LDPC codes is more complicated since a vector of messages instead of a single message is passed along each edge of the associated Tanner graph. Layered decoding can be employed to simplify LDPC decoding. However, there is extra latency between the decoding of layers caused by check node processing, message permutation and updating when applied to NB-LDPC codes. In this paper, a novel scheduling scheme is developed to eliminate the extra latency for the Min-max decoding of quasi-cyclic (QC) NB-LDPC codes using trellis-based check node processing. Assume that each row of sub-matrices in the parity check matrix of a QCNB-LDPC code is divided into two layers, the proposed scheme can reduce the decoding latency by a factor of around (2dc+ 5)/2dc, where dcis the check node degree. It leads to significant speedup when dcis not large. Moreover, the area overhead of the proposed scheme is less than 10%.

DOI: 10.1109/apccas.2010.5774734

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