This work investigated the performance of a newly developed protograph-based low-density parity-check code (LDPC) families belonging to accumulate-repeat-4-jagged-accumulate codes. The proposed code has hierarchical irregularity and quasi-cyclic property that retains it to be suitable for fast encoder and decoder implementation. The code used in this work is a rate-compatible linearly punctured code. The modified iterative decoding algorithm as mentioned in the literature is used along with a newly proposed encoder and simulation has been done for proposed LDPC coded orthogonal frequency division multiplexing (OFDM) link over wireless and optical wireless channels with hard- and soft-decision decoding. The code relates to new methods for designing rate-compatible families of protographs of different rates, all having the linear minimum distance property showing small performance degradation compared with the threshold. The parity-check matrix is composed of small identical modules to reduce the routing complexity of the decoder. The main essence of this code lies in the fact that LDPC codes of arbitrarily large size can be built by expanding from individual protographs or rate-compatible protograph families.
This work investigated the performance of a newly developed protograph-based low-density parity-check code (LDPC) families belonging to accumulate-repeat-4-jagged-accumulate codes. The proposed code has hierarchical irregularity and quasi-cyclic property that retains it to be suitable for fast encoder and decoder implementation. The code used in this work is a rate-compatible linearly punctured code. The modified iterative decoding algorithm as mentioned in the literature is used along with a newly proposed encoder and simulation has been done for proposed LDPC coded orthogonal frequency division multiplexing (OFDM) link over wireless and optical wireless channels with hard- and soft-decision decoding. The code relates to new methods for designing rate-compatible families of protographs of different rates, all having the linear minimum distance property showing small performance degradation compared with the threshold. The parity-check matrix is composed of small identical modules to reduce the routing complexity of the decoder. The main essence of this code lies in the fact that LDPC codes of arbitrarily large size can be built by expanding from individual protographs or rate-compatible protograph families.
This paper provides a construction method for low-rate low density parity check codes. Inspired by recently proposed accumulate-repeat-accumulate (ARA) codes, and hybrid concatenated codes, in this paper we extend the construction to low rates. Such codes can be viewed as hybrid concatenations of simple modules such as accumulators, repetition codes, differentiators, and punctured single parity check codes. These codes constitute a subclass of LDPC codes with very fast encoder structure. They also have a projected graph or protograph representation that allows for high-speed decoder implementation. Based on density evolution, we show through some examples that low iterative decoding thresholds close to the channel capacity limits can be achieved, as the block size goes to infinity. Iterative decoding simulation results for short blocks are provided for a few examples that show near-capacity performance and very low error floor
We propose a novel design of rate-compatible protograph-based low-density parity-check code families that can cover a wide range of code rates. In contrast to traditional method of lifting, our lifting method use a combination of different circulant matrix sizes for the base protograph and accumulator to increase the number of achievable rates. We apply this method to an existing code family called AR4JA, which can offer variable rates of R = n+1/n+2 by process of extension. The proposed codes namely mixed-circulant rate-compatible protograph code (MCRC-PC) can reduce the rate step within the AR4JA family. We show that the proposed codes can also retain many of the favorable properties of protograph codes such as a fast encoder and decoder implementation. A set of length k=1024 MCRC-PC codes is designed with decoding thresholds obtained from multi-edge type density evolution, and simulation results show that the rate compatible code family can achieve good performance under message passing decoding algorithm.
Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat-accumulate (S-IRA) codes. These S-IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S-IRA codes are suitable for rate-compatible code family design and a multi-rate code family has been designed which may be implemented with a single encoder/decoder.The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi-cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant-based decoder and a protograph-based decoder. By focusing on the protograph-based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi-cyclic LDPC codes, including the S-IRA codes. A universal decoder architecture is also proposed which is capable of decoding of an arbitrary LDPC code, quasi-cyclic or not. Finally, we studied the low-floor problem by focusing on one example S-IRA code. We identified the weaknesses of the code and proposed several techniques to lower the error floor. We successfully demonstrated in hardware that it is possible to lower the floor substantially by encoder and decoder modifications, but the best solution appeared to be an outer BCH code.
In this paper, we present a method of constructing new families of LDPC block code ensembles formed by terminating irregular protograph-based LDPC convolutional codes. Using the accumulate-repeat-by-4-jagged-accumulate (AR4JA) protograph as an example, a density evolution analysis for the binary erasure channel shows that this flexible design technique gives rise to a large selection of LDPC block code ensembles with varying code rates and thresholds close to capacity. Further, by means of an asymptotic weight enumerator analysis, we show that all the ensembles in this family also have minimum distance that grows linearly with block length, i.e., they are asymptotically good.
Over time-varying wireless channel,it is necessary for error-correction codes to be rate-compatible.Protograph LDPC codes can achieve rate-compatibility through and extending;and solve the problem that the encoders of tradition LDPC codes are more complex.With the AR4JA code which can be represented by protograph,we construct a rate-compatible family of AR4JA codes with rates ranging from 0.5 to 0.8 using the algorithm of puncturing node by node.To obtain the lower rates from 0.5 to 0.25,matrix expansion is also used.Simulation results over AWGN channel show that using both and extending we can construct rate-compatible family of AR4JA codes which do not suffer from error floor when BER is 10-6.
In this paper we propose an innovative LDPC coded modulation scheme. We design binary low density parity check (LDPC) codes that are combined with high level modulations such as 8PSK and 16QAM with and without a channel interleaver. At the receiver a demapper transforms the received inphase and quadrature samples to produce reliability information that feeds the binary LDPC decoder. Using this scheme, the same encoder and decoder can support various modulations. Analysis of ensemble average weight enumerators shows that the minimum distance of the proposed LDPC codes grows linearly with block size. Our constructions are based on protograph structures that support high-speed decoder implementations. We also show that precoding can be used to lower the threshold of LDPC codes. The decoding thresholds of the proposed codes, which have linearly increasing minimum distance in block size, outperform that of regular LDPC codes. Furthermore, a family of low to high rate codes, with thresholds that adhere closely to their respective channel capacity thresholds, is presented. For maximum variable node degree 6, the iterative decoding thresholds of these codes outperform the best known unstructured irregular LDPC codes reported in the literature. Iterative decoding simulation results are provided for BPSK, QPSK, 8PSK, and 16QAM modulations over the additive white Gaussian noise channel. FPGA simulation results for the proposed LDPC codes with input block size of 4096 and QPSK modulation (throughput=1 bps/Hz) show that a frame error rate of 10-8and a bit error rate of 10-10can be achieved at Eb/No=1.50 dB