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International Conference on Advanced Computing and Communication Systems (ICACCS)

An analytical approach to the performance of Low Density Parity Check Codes

R. Lakshmi, Tilty Tony, Abin Johns Raju

Published Dec 1, 2013• 5 citations
Publisher

Abstract

Low Density Parity Check Codes (LDPC) is a class of linear block codes best suited for forward error control in communication systems. When compared with other codes, LDPC codes have significant performance gain, which can be turned to an increase of the coverage range or a reduction of transmission power. Hence a convenient and practical receiver is obtained. The analysis done in this paper is based on the Bit Error Rate of the decoded output. The factors considered for the analysis are multiple code rate, different number of iterations and various decoding schemes. For lower code rate, soft decision decoding and increased number of iterations LDPC codes yields a better performance.

DOI
10.1109/icaccs.2013.6938732

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Low Density Parity Check Codes (LDPC) is a class of linear block codes best suited for forward error control in communication systems. When compared with other codes, LDPC codes have significant performance gain, which can be turned to an increase of the coverage range or a reduction of transmission power. Hence a convenient and practical receiver is obtained. The analysis done in this paper is based on the Bit Error Rate of the decoded output. The factors considered for the analysis are multiple code rate, different number of iterations and various decoding schemes. For lower code rate, soft decision decoding and increased number of iterations LDPC codes yields a better performance.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
Low Density Parity Check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. In many digital communication systems, these codes have strong competitors of turbo codes for error control. LDPC codes performance depends on the excellent design of parity check matrix and many diverse research methods have been used by different study groups to evaluate the performance. Unlike many other classes of codes, LDPC codes are already equipped with a fast, probabilistic decoding algorithm. This makes LDPC codes not only attractive from a theoretical point of view, but also very suitable for practical applications. This paper throws hard decision and soft decision algorithm of LDPC. The hard decision algorithm contains Bit flipping algorithm and Soft decoding algorithm contains Sum product algorithm which is used to correct burst error. Sum Product algorithm is also called as belief propagation. Bit flipping and Sum Product algorithms are explained and can be implemented for the generated parity check matrix of (1016x508) for LDPC code with code rate 1/2.
The Low Density Parity Check (LDPC) are direct codes, which are true block and Shannon Limit codes.These codes are attained least error floors of data bits for data transfer applications used in communication systems.However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time.This results the reduction of decoding time, low decoding latency, complexity and as well as least error floorings in communication, when the transmitted data contains multiple error bits.This paper is proposed to represent the majority logic decoding/detecting of LDPC codes.This paper proposes the Generation of Originator and Parity estimated matrices for the Binary LDPC Codes.Here, the proposed techniques are hard decision decrypting and soft decision decrypting schemes.These schemes uses majority logic decoding based on the data transmission and reception in communication channel.This paper also elaborates the effective calculation of Euclidean distance and algorithm for constructing the LDPC codes.
Low density parity checking codes (LDPC) are one of the most important issues in coding theory at present. LDPC-code are a type of linear-block LDPC-codes. Channel coding might be considered as the finest conversant and most potent components of cellular communications systems, that was employed for transmitting errors corrections imposed by noise, fading and interfering. LDPC-codes are advanced coding gain, i.e., new area in coding. the performances of LDPC-code are similar to the Shannon-limiting, this led to the usage of decoding in several applications in digital communications systems, like DVB-S2 and WLAN802.1..This paper aims to know what is LDPC,what its application and introduce encoding algorithms that gives rise to a linear encoding time and also show that the regular and irregular LDPC performance and also introduce different methods for decoding LDPC. I discuss in detail LDPC decoding algorithm: bit flipping algorithm, as a type from hard decision .belief propagation algorithm, sum product algorithm and minimum sum algorithm as examples from soft decision .I expect that at least some students or researchers involved in researching LDPC codes would find this paper helpful.
Channel coding technique is a fundamental building block in any modern communication system to realize reliable, fast, and secure data transmission. At the same time, it is a challenging and crucial task, as the data transmission happens in a channel where noise, fading, and other impairments are present. The Low-Density Parity-Check (LDPC) codes give substantial results close to the Shannon limit when the complexity and processing delay time are unlimited. In this paper, the performance of the LDPC decoding with four algorithms was investigated. The investigated four algorithms were Belief Propagation (BP), Layered Belief Propagation (LBP), Normalized min-sum (NMS), and Offset min-sum (OMS). These algorithms were examined for code rates ranging from 1/3 to 9/10 and message block lengths (64, 512, 1024, and 5120) bits. The simulation results revealed the flexibility of these decoders in supporting these code rates and block lengths, which enables their usage in a wide range of applications and scenarios for fifth-generation (5G) wireless communication. In addition, the effect of the maximum number of decoding iterations on the error correction performance was investigated, and a gain of 5.6 dB can be obtained by using 32 decoding iterations at BER=2*10-3 instead of one decoding iteration. The results showed that the decoders performed better for longer message blocks than for short message blocks, and less power was required for transmitting longer messages. Finally, the comparison results of their performance in terms of bit error rate (BER) under the same conditions showed a gain of 0.8 dB using LBP at BER= 10-5 compared with the NMS decoding algorithm.