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IEEE Transactions on Applied Superconductivity

High-frequency clock operation of Josephson 256-word×16-bit RAMs

Shuichi Nagasawa, Hideaki Numata, Y. Hashimoto, Shuichi Tahara

Published Jun 1, 1999• 47 citations
Publisher

Abstract

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

DOI
10.1109/77.783834

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A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.
We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables high-frequency clock operation up to 10 GHz. The SLASH RAM is composed of ac-powered latching devices and dc-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16/spl times/16 matrix array of vortex transitional memory cells, SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We confirmed that the 256-bit SLASH RAM block functioned successfully.
We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.
A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
An experimental memory model for investigating the feasibility of a 16K RAM memory with Josephson junctions was fabricated and tested. There are nearly 4500 Josephson junctions in the design which includes array, line drivers, and address decoders. Storage element is a single flux-quantum (SFQ) cell arranged in a 2K array. Drivers and decoders are based on the principle of current steering in superconducting loops, which is a medium speed but low power approach. The measured read-access time of the model is approximately 10 ns. Power dissipation of the unselected chip is zero, whereas for a read/write cycle time of 30 ns, it amounts to about 10 /spl mu/W. Results indicate that a 16K chip is feasible electrically. The estimated access time and power dissipation are 15 ns and 40 /spl nu/W, respectively.
We present the design and test results of components for a superconductor Cryogenic Random Access Memory (CRAM). The 16-Kb RAM design consists of four 4-Kb sub-arrays (blocks) with a 400 ps access time (latency) and a 100 ps cycle time (throughput). Each 4-Kb RAM block comprises a row-accessed 32/spl times/128 memory cell array, bipolar line drivers, row decoders, and column sense circuits. The implementation of specially designed distributed Josephson junctions in the sensing circuits reduces the overall size of the blocks and allows the use of smaller dc control currents.
We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology. In the microprocessor designed here, called CORE1/spl alpha/6, a simple bit-serial architecture with seven instructions was employed. In the CORE1/spl alpha/6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections. The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1/spl alpha/6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1/spl alpha/6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS).