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Lecture notes in computer science

Architecture of a Quantum Multicomputer Implementing Shor’s Algorithm

Rodney Van Meter, William J. Munro, Kae Nemoto

Published Jan 1, 2008• 10 citations
Publisher
DOI
10.1007/978-3-540-89304-2_10

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The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor's algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation. My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture. Calculations show that these algorithms are one million times and thirteen thousand times faster, when factoring a 6,000-bit number, depending on architecture. Extending to the quantum multicomputer, five different qubus interconnect topologies are considered, and two forms of carry-ripple adder are found to be the fastest for a wide range of performance parameters. The links in the quantum multicomputer are serial; parallel links would provide only very modest improvements in system reliability and performance. Two levels of the Steane [[23,1,7]] error correction code will adequately protect our data for factoring a 1,024-bit number even when the qubit teleportation failure rate is one percent.

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The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor's algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation. My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture. Calculations show that these algorithms are one million times and thirteen thousand times faster, when factoring a 6,000-bit number, depending on architecture. Extending to the quantum multicomputer, five different qubus interconnect topologies are considered, and two forms of carry-ripple adder are found to be the fastest for a wide range of performance parameters. The links in the quantum multicomputer are serial; parallel links would provide only very modest improvements in system reliability and performance. Two levels of the Steane [[23,1,7]] error correction code will adequately protect our data for factoring a 1,024-bit number even when the qubit teleportation failure rate is one percent.

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Architecture of a Quantum Multicomputer

Rodney Van Meter, William J. Munro, Kae Nemoto

We have created the architecture of a quantum multicomputer and analyzed its performance for running Shor’s algorithm for factoring large numbers. In this paper, we combine fault-tolerance techniques with performance goals for our architecture, which uses a linear interconnect and six logical qubits per node. Our performance target of factoring a 1,024-bit number in one month requires teleporting 6.2 logical qubits per second on each link in the system, which translates to 3,300 physical teleportations per second on each link. A qubus-based interconnect generates Bell pairs of intermediate fidelity that must be purified. Starting from a Bell state with fidelity F = 0.638, as a qubus-based cavity QED interconnect might generate with a qubit-to-qubit loss of 3.4dB, about 1.5 million physical entanglement attempts per second are enough to reach this level of performance.

•Jan 1, 2007•0 citations
The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor's algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation. My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture. Calculations show that these algorithms are one million times and thirteen thousand times faster, when factoring a 6,000-bit number, depending on architecture. Extending to the quantum multicomputer, five different qubus interconnect topologies are considered, and two forms of carry-ripple adder are found to be the fastest for a wide range of performance parameters. The links in the quantum multicomputer are serial; parallel links would provide only very modest improvements in system reliability and performance. Two levels of the Steane [[23,1,7]] error correction code will adequately protect our data for factoring a 1,024-bit number even when the qubit teleportation failure rate is one percent.
The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor's algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation. My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture. Calculations show that these algorithms are one million times and thirteen thousand times faster, when factoring a 6,000-bit number, depending on architecture. Extending to the quantum multicomputer, five different qubus interconnect topologies are considered, and two forms of carry-ripple adder are found to be the fastest for a wide range of performance parameters. The links in the quantum multicomputer are serial; parallel links would provide only very modest improvements in system reliability and performance. Two levels of the Steane [[23,1,7]] error correction code will adequately protect our data for factoring a 1,024-bit number even when the qubit teleportation failure rate is one percent.
We have created the architecture of a quantum multicomputer and analyzed its performance for running Shor’s algorithm for factoring large numbers. In this paper, we combine fault-tolerance techniques with performance goals for our architecture, which uses a linear interconnect and six logical qubits per node. Our performance target of factoring a 1,024-bit number in one month requires teleporting 6.2 logical qubits per second on each link in the system, which translates to 3,300 physical teleportations per second on each link. A qubus-based interconnect generates Bell pairs of intermediate fidelity that must be purified. Starting from a Bell state with fidelity F = 0.638, as a qubus-based cavity QED interconnect might generate with a qubit-to-qubit loss of 3.4dB, about 1.5 million physical entanglement attempts per second are enough to reach this level of performance.