Millions of qubits need to be employed in a quantum computer to achieve a fault-tolerant quantum operation. To reduce the complexity in such a large-scale system, the control and readout circuitries have been proposed to be placed at the 4 K stage of dilution refrigerators [1]. CMOS technology is commonly used to leverage its scaling to enable large integration of control and readout circuitries with qubits. However, the high-fidelity readout operations require low noise amplifiers (LNAs) with a noise temperature of a few Kelvins. This necessitates the usage of HEMT and parametric amplifiers [2]. Recently reported CMOS LNAs are still far away from attaining such good performance [3–5]. Thus, this is one of the greatest challenges on the way to the fully integrated CMOS readout. Additionally, due to the limited cooling power of dilution refrigerators, low-power solutions are needed for achieving a very good noise performance at 4 K. This paper presents a 28 nm CMOS LNA for qubit readout, which achieves an order of magnitude power reduction compared to its CMOS counterparts while still providing a similar good noise Figure (NF) performance at 4 K.Millions of qubits need to be employed in a quantum computer to achieve a fault-tolerant quantum operation. To reduce the complexity in such a large-scale system, the control and readout circuitries have been proposed to be placed at the 4 K stage of dilution refrigerators [1]. CMOS technology is commonly used to leverage its scaling to enable large integration of control and readout circuitries with qubits. However, the high-fidelity readout operations require low noise amplifiers (LNAs) with a noise temperature of a few Kelvins. This necessitates the usage of HEMT and parametric amplifiers [2]. Recently reported CMOS LNAs are still far away from attaining such good performance [3–5]. Thus, this is one of the greatest challenges on the way to the fully integrated CMOS readout. Additionally, due to the limited cooling power of dilution refrigerators, low-power solutions are needed for achieving a very good noise performance at 4 K. This paper presents a 28 nm CMOS LNA for qubit readout, which achieves an order of magnitude power reduction compared to its CMOS counterparts while still providing a similar good noise Figure (NF) performance at 4 K.

IEEE Asian Solid-State Circuits Conference (A-SSCC)Nov 7, 20217 citations

C-8-11 SFQ/CMOSハイブリッドメモリの多ビットデータ入力化の検討(C-8.超伝導エレクトロニクス,一般セッション)

謙太矢口, 啓太桑原, 賢珠陳 +1 more

電子情報通信学会総合大会講演論文集Feb 28, 20110 citations

An Ultrawideband Cryogenic LNA in 40-nm CMOS for Multiple Spin/Superconducting Qubit Readout

Mahesh Kumar Chaubey, Yin‐Cheng Chang, Po‐Chang Wu +2 more

This letter presents an ultrawideband cryogenic low-noise amplifier (LNA) with current reuse and stacked inverter-based input-referred noise (IRN) cancellation in 40-nm CMOS. The first stage utilizes an IRN reduction high- $Q$ gate inductor with current reuse, a stacked inverter-based shunt-resistive feedback input stage, and a cryogenically aware back-gate biasing technique to regulate the threshold voltage under cryogenic operation. The second stage is the common-source (CS) main amplifier, followed by a cascode current-reuse auxiliary amplifier to suppress the channel thermal noise of the main amplifier. The third stage is the current-reuse CS inverter-based postamplifier buffer stage. At 4 K, the LNA achieves a measured peak gain ( ${S} _{21}$ ) of 37 dB, with a large 3-dB bandwidth (BW) from 0.15 to 8 GHz and aNFminof 0.4 dB at 3.2 GHz under ${P} _{\mathrm {DC}}$ of 13.2 mW. To our knowledge, the proposed LNA achieves the BW bandwidth and the figure of merit (FoM) among the highest compared to published CMOS LNAs operating at 4 K. The proposed LNA is suitable for both spin and superconducting qubit readout.This letter presents an ultrawideband cryogenic low-noise amplifier (LNA) with current reuse and stacked inverter-based input-referred noise (IRN) cancellation in 40-nm CMOS. The first stage utilizes an IRN reduction high-$Q$gate inductor with current reuse, a stacked inverter-based shunt-resistive feedback input stage, and a cryogenically aware back-gate biasing technique to regulate the threshold voltage under cryogenic operation. The second stage is the common-source (CS) main amplifier, followed by a cascode current-reuse auxiliary amplifier to suppress the channel thermal noise of the main amplifier. The third stage is the current-reuse CS inverter-based postamplifier buffer stage. At 4 K, the LNA achieves a measured peak gain (${S} _{21}$) of 37 dB, with a large 3-dB bandwidth (BW) from 0.15 to 8 GHz and aNFminof 0.4 dB at 3.2 GHz under${P} _{\mathrm {DC}}$of 13.2 mW. To our knowledge, the proposed LNA achieves the BW bandwidth and the figure of merit (FoM) among the highest compared to published CMOS LNAs operating at 4 K. The proposed LNA is suitable for both spin and superconducting qubit readout.

IEEE Microwave and Wireless Technology LettersNov 24, 20252 citations

A system design approach toward integrated cryogenic quantum control systems

Mridula Prathapan, Peter R. Müeller, David Heim +8 more

In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.

arXiv:2211.02081IEEE Workshop on Low Temperature Electronics (WOLTE)Jun 6, 20224 citations

C-8-13 SFQ/CMOSハイブリッドメモリのシリアルデータ入力化の検討(C-8.超伝導エレクトロニクス,一般セッション)

謙太矢口, 悠史岡本, 賢珠陳 +3 more

電子情報通信学会総合大会講演論文集Mar 2, 20100 citations

Q

gate inductor with current reuse, a stacked inverter-based shunt-resistive feedback input stage, and a cryogenically aware back-gate biasing technique to regulate the threshold voltage under cryogenic operation. The second stage is the common-source (CS) main amplifier, followed by a cascode current-reuse auxiliary amplifier to suppress the channel thermal noise of the main amplifier. The third stage is the current-reuse CS inverter-based postamplifier buffer stage. At 4 K, the LNA achieves a measured peak gain (

{S} _{21}

) of 37 dB, with a large 3-dB bandwidth (BW) from 0.15 to 8 GHz and aNFminof 0.4 dB at 3.2 GHz under

{P} _{\mathrm {DC}}

of 13.2 mW. To our knowledge, the proposed LNA achieves the BW bandwidth and the figure of merit (FoM) among the highest compared to published CMOS LNAs operating at 4 K. The proposed LNA is suitable for both spin and superconducting qubit readout.