Low-density parity-check (LDPC) codes are widely used as error correction codes in new generation digital TV standards, such as the second generation of terrestrial digital video broadcasting standard (DVB-T2), Advanced Television Systems Committee (ATSC) 3.0, etc. The nonlinear belief propagation (BP) algorithm has excellent decoding performance for LDPC codes, but is often simplified in hardware implementations by linear min-sum (MS) algorithm due to its high complexity. This simplification also leads to over-estimation problems, which can be corrected by adding factors in conventional algorithms (e.g., normalized min-sum (NMS), offset min-sum (OMS), and variable scaling normalized min-sum (VMS) algorithms). However, the correction factors of these modified MS algorithms cannot adapt to different channels and modulations, and the performance needs further improvement. In this paper, the concepts of over-estimation value (OEV) and over-estimation rate (OER) are introduced to describe the over-estimation problem of the MS algorithm. Then, under the guidance of OEV and OER, a polygonal line min-sum (PMS) algorithm with correction factors adapted to different channels and modulations is proposed according to LLR distribution. Following the properties of OEV and OER, PMS algorithm is further simplified into Simplified PMS (SPMS) algorithm. LDPC codes from ATSC 3.0 are adopted in this paper to evaluate SPMS algorithm in comparison with the conventional algorithms. Extensive simulation results show that the SPMS algorithm for ATSC 3.0 LDPC decoder has at most 1.61dB, 0.24dB and 0.36dB gain over NMS, OMS and VMS algorithms respectively when frame error rate (FER) is at 10−4level over additive white Gaussian noise (AWGN) channel with QPSK modulation. More importantly, the simulation results show that the SPMS algorithm can achieve much better performance than these modified MS algorithms over AWGN and Rayleigh channel with higher-order modulations or under limited maximum iteration number.Low-density parity-check (LDPC) codes are widely used as error correction codes in new generation digital TV standards, such as the second generation of terrestrial digital video broadcasting standard (DVB-T2), Advanced Television Systems Committee (ATSC) 3.0, etc. The nonlinear belief propagation (BP) algorithm has excellent decoding performance for LDPC codes, but is often simplified in hardware implementations by linear min-sum (MS) algorithm due to its high complexity. This simplification also leads to over-estimation problems, which can be corrected by adding factors in conventional algorithms (e.g., normalized min-sum (NMS), offset min-sum (OMS), and variable scaling normalized min-sum (VMS) algorithms). However, the correction factors of these modified MS algorithms cannot adapt to different channels and modulations, and the performance needs further improvement. In this paper, the concepts of over-estimation value (OEV) and over-estimation rate (OER) are introduced to describe the over-estimation problem of the MS algorithm. Then, under the guidance of OEV and OER, a polygonal line min-sum (PMS) algorithm with correction factors adapted to different channels and modulations is proposed according to LLR distribution. Following the properties of OEV and OER, PMS algorithm is further simplified into Simplified PMS (SPMS) algorithm. LDPC codes from ATSC 3.0 are adopted in this paper to evaluate SPMS algorithm in comparison with the conventional algorithms. Extensive simulation results show that the SPMS algorithm for ATSC 3.0 LDPC decoder has at most 1.61dB, 0.24dB and 0.36dB gain over NMS, OMS and VMS algorithms respectively when frame error rate (FER) is at 10−4level over additive white Gaussian noise (AWGN) channel with QPSK modulation. More importantly, the simulation results show that the SPMS algorithm can achieve much better performance than these modified MS algorithms over AWGN and Rayleigh channel with higher-order modulations or under limited maximum iteration number.

IEEE Transactions on BroadcastingAug 23, 20217 citations

Research on high performance LDPC decoder

Wen Ji, 32134

Jan 1, 20111 citation

Low-complexity LDPC decoding algorithms for ultra-high-order modulated signals

Hongjun Zhu, Meiyu Fu, Chen Hou +1 more

Low-complexity decoding algorithms and ultra-high-order modulation formats are necessary to meet data rate requirements in excess of 1 Tbps. The information bottleneck algorithm has been effectively applied to the LDPC decoding algorithm in recent years, and its performance is comparable to that of the double-precision information propagation technique. However, the application of information bottleneck decoding algorithms in ultra-high order modulation forms has received little attention. Furthermore, the number of table lookups required for a single decoding loop is square to the node degree, which is undesirable for optical communications. We present a low-complexity LDPC decoding technique for ultra-high-order modulated signals in this study. First, the algorithm employs multivariate covariates to build an information bottleneck framework, which introduces the processing required for applying the information bottleneck algorithm to 1024-QAM signals and the requirement of combining higher-order modulation formats with LDPC codes. The technique makes use of a bidirectional recursive network and the symmetry of quantized information to reuse the same set of tables, considerably reducing the number of table lookup operations required in the decoding process. Constructing a coherent optical communication system with 1024-QAM signals proves that the proposed algorithm can operate effectively. The performance sacrifice of 0.2 ∼ 0.3 dB reduces the number of table lookup operations required for decoding from square to linear magnitude, which greatly reduces the decoding time required in optical communication.Low-complexity decoding algorithms and ultra-high-order modulation formats are necessary to meet data rate requirements in excess of 1 Tbps. The information bottleneck algorithm has been effectively applied to the LDPC decoding algorithm in recent years, and its performance is comparable to that of the double-precision information propagation technique. However, the application of information bottleneck decoding algorithms in ultra-high order modulation forms has received little attention. Furthermore, the number of table lookups required for a single decoding loop is square to the node degree, which is undesirable for optical communications. We present a low-complexity LDPC decoding technique for ultra-high-order modulated signals in this study. First, the algorithm employs multivariate covariates to build an information bottleneck framework, which introduces the processing required for applying the information bottleneck algorithm to 1024-QAM signals and the requirement of combining higher-order modulation formats with LDPC codes. The technique makes use of a bidirectional recursive network and the symmetry of quantized information to reuse the same set of tables, considerably reducing the number of table lookup operations required in the decoding process. Constructing a coherent optical communication system with 1024-QAM signals proves that the proposed algorithm can operate effectively. The performance sacrifice of 0.2 ∼ 0.3 dB reduces the number of table lookup operations required for decoding from square to linear magnitude, which greatly reduces the decoding time required in optical communication.

Optics ExpressNov 14, 20232 citations

Fast-convergence architectures and low-complexity algorithms for LDPC decoding

Massimo Rovini, Luca Fanucci, Francesco Rossi

Jan 1, 20060 citations

Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes

Anuj Verma, Rahul Shrestha

This article proposes a simplified offset min-sum (SOMS) decoding algorithm for the QC-LDPC codes. It is an implementation-friendly algorithm based on a new logarithmic-likelihood-ratio (LLR) grouping technique that alleviates the computational complexity of the QC-LDPC channel-decoder. This work also presents a parallel and hardware-efficient architecture of the QC-LDPC decoder based on the suggested SOMS algorithm. Additional architectural transformations have been carried out to reduce the routing complexity of the proposed decoder and deliver lower latency and higher throughput. Comprehensive performance analysis of the SOMS algorithm has been presented under various scenarios based on the specifications of the 5G-NR standard. It shows that the suggested SOMS algorithm delivers an adequate FER of 10 $^{-5}$ at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368$- $26112 bits and 1/3$ - $8/9, respectively. This FPGA implementation of the proposed QC-LDPC decoder delivers a peak throughput of 13.3 Gbps and latency of 0.77$ \mu$s while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.This article proposes a simplified offset min-sum (SOMS) decoding algorithm for the QC-LDPC codes. It is an implementation-friendly algorithm based on a new logarithmic-likelihood-ratio (LLR) grouping technique that alleviates the computational complexity of the QC-LDPC channel-decoder. This work also presents a parallel and hardware-efficient architecture of the QC-LDPC decoder based on the suggested SOMS algorithm. Additional architectural transformations have been carried out to reduce the routing complexity of the proposed decoder and deliver lower latency and higher throughput. Comprehensive performance analysis of the SOMS algorithm has been presented under various scenarios based on the specifications of the 5G-NR standard. It shows that the suggested SOMS algorithm delivers an adequate FER of 10$^{-5}$at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368$-$26112 bits and 1/3$-$8/9, respectively. This FPGA implementation of the proposed QC-LDPC decoder delivers a peak throughput of 13.3 Gbps and latency of 0.77$\mu$s while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.

IEEE Transactions on Vehicular TechnologySep 2, 202238 citations

^{-5}

at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368$-

26112 bits and 1/3

8/9, respectively. This FPGA implementation of the proposed QC-LDPC decoder delivers a peak throughput of 13.3 Gbps and latency of 0.77

\mu$s while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.