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arXiv:2610.10490

Standard estimators cannot represent fault-tolerant workloads at measured error rates: evaluated, evidence-based uncertainty for quantum resource estimation

Furqan Nasir, Sher Jeel Ahmad

quant-phSubmitted Oct 7, 2026• Announced Oct 8, 2026• 0 citations
arXivHTMLPDF

Abstract

Estimates of the quantum resources needed to run fault-tolerant algorithms are almost always reported as single numbers, even though they rest on uncertain hardware parameters and on cost models that disagree. We present an open, tool-agnostic framework that propagates evidence-based priors over fault-tolerant hardware parameters through five surface-code cost models, adds correlated-input sensitivity analysis, and evaluates the resulting intervals with a pre-registered three-layer protocol. Applied to RSA-2048, ECC-256, AES-256, and a Hubbard-model simulation on a superconducting surface-code architecture, it produces three coupled findings that together undermine the single-number convention. Propagating the error rates hardware has actually demonstrated, whose median across five large-array devices is about 4 x 10^-3 rather than the conventional 10^-3, widens the 90% physical-qubit interval to roughly forty times and lifts its median about 4.6 times above the conventional point estimate. Against the same inputs, five independently structured cost models, including two third-party estimators (the Azure Quantum Resource Estimator and Qualtran) that agree with each other to within about ten percent, disagree by a stable factor of two, a structural uncertainty that no single tool reveals. Most consequentially, both third-party estimators exceed their representable envelope for 80 to 100 percent of the evidence-based parameter space, and the AES-256 gate count overflows one tool's counter outright, so these workloads cannot be represented at measured error rates at all. The optimistic convention conceals every one of these effects. The uncertainty machinery we use is standard. The contribution is its evidence-based application, the pre-registered evaluation, and the finding that standard tools break down precisely where hardware operates.

Comments
22 pages, 4 figures

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Estimates of the quantum resources needed to run fault-tolerant algorithms are almost always reported as single numbers, even though they rest on uncertain hardware parameters and on cost models that disagree. We present an open, tool-agnostic framework that propagates evidence-based priors over fault-tolerant hardware parameters through five surface-code cost models, adds correlated-input sensitivity analysis, and evaluates the resulting intervals with a pre-registered three-layer protocol. Applied to RSA-2048, ECC-256, AES-256, and a Hubbard-model simulation on a superconducting surface-code architecture, it produces three coupled findings that together undermine the single-number convention. Propagating the error rates hardware has actually demonstrated, whose median across five large-array devices is about 4 x 10^-3 rather than the conventional 10^-3, widens the 90% physical-qubit interval to roughly forty times and lifts its median about 4.6 times above the conventional point estimate. Against the same inputs, five independently structured cost models, including two third-party estimators (the Azure Quantum Resource Estimator and Qualtran) that agree with each other to within about ten percent, disagree by a stable factor of two, a structural uncertainty that no single tool reveals. Most consequentially, both third-party estimators exceed their representable envelope for 80 to 100 percent of the evidence-based parameter space, and the AES-256 gate count overflows one tool's counter outright, so these workloads cannot be represented at measured error rates at all. The optimistic convention conceals every one of these effects. The uncertainty machinery we use is standard. The contribution is its evidence-based application, the pre-registered evaluation, and the finding that standard tools break down precisely where hardware operates.
Resource estimation is a significant challenge in evaluating fault tolerant quantum computers. Existing approaches often rely on either fixed architectural assumptions or coarse analytical models that fail to capture the interaction between hardware constraints and circuit compilation. This challenge is particularly acute for neutral atom quantum computers, where architectural features such as atom movement, measurement zones, and multi-species arrays introduce a broad design space for implementing fault tolerant computation. Addressing the need for a tighter feedback loop between hardware design and practical application development, we present a compilation-driven framework for quantum resource estimation that translates arbitrary quantum circuits into logical primitive operations with known physical resource costs. This framework allows for easily configurable hardware assumptions that enable rapid comparison of different architectural design choices. We apply our approach to two early fault tolerant quantum simulation and optimization workloads, assuming the use of the surface code, revealing several architectural trends. While the production of magic states continues to be the dominant source of overhead for these benchmarks, access to movement can save time on cultivation and important transversal gates. As problem size grows, routing and qubit movement become dominant bottlenecks, highlighting the need for movement-aware compiler optimizations and frugal routing strategies. Finally, our results suggest that neutral atom architectures combining dual-species arrays with controlled qubit movement offer a promising path toward near-term advantage on fault tolerant devices.
Fault-tolerant quantum computing is progressing from demonstrations of individual logical components toward the execution of useful quantum algorithms on large-scale error-corrected processors. Realizing this transition requires co-design across algorithms, fault-tolerant implementations, and hardware resources. Here we develop an algorithm-to-execution framework for low-cost surface-code quantum computing that carries the structure of a computation from hierarchical logical descriptions to circuit-specific spatial organization, non-Clifford resource planning, and physical resource evaluation. We apply the framework to twenty benchmark circuits spanning seven algorithm families and to a hierarchically reconstructed application-scale elliptic-curve discrete-logarithm workload. Under the stated error and resource-supply models, combining circuit-specific layouts with hybrid non-Clifford implementation reduces space--time volume by up to 12.70x relative to an all-synthesis Litinski fast-block baseline. Circuit-specific layouts reduce both modeled runtime and space--time volume in eighteen benchmarks, while the remaining two retain the fast layout. These results show that the physical cost of fault-tolerant computation emerges from the interaction between algorithm structure, error-corrected implementation, and hardware organization rather than from aggregate logical resource counts alone.
Scaling fault-tolerant superconducting quantum computers will likely require distributed architectures built from multiple manufacturable quantum processing units. A central question is whether noisy and slow inter-chip operations impose substantial spacetime overhead or orchestration burdens compared with monolithic architectures. To answer this question, we present a hardware-grounded architectural co-design together with a comprehensive resource-estimation protocol for surface-code-based modular processors. The design confines inter-chip latency and noise to module boundaries, preventing slow, noisy links from inducing prohibitive spacetime overhead or becoming a global orchestration bottleneck. The resource-estimation protocol integrates hardware constraints and circuit-level error-correction performance into utility-scale algorithmic cost estimates, enabling a controlled assessment of different architectures. Using RSA-2048 factorization as a demanding benchmark, we estimate resources under experimentally anchored parameters and realistic superconducting hardware constraints. Compared with a large, ideal monolithic baseline, the resulting distributed architecture requires only modest additional resource overhead in both qubit count and execution time. More importantly, the overhead is nearly scale-invariant across a broad module-capacity window, decoupling chip size from global performance. This decoupling turns module capacity from a finely tuned architectural parameter into a flexible engineering degree of freedom, allowing chip sizes to be set by manufacturability and control-packaging constraints rather than architectural fine-tuning. These results establish a viable route to distributed fault-tolerant superconducting quantum computation that scales without prohibitive resource growth or heavy orchestration burden.
Quantum error correction codes are essential for fault-tolerant quantum computing. They are a method of detecting and correcting errors in a quantum computer by encoding logical qubits across multiple physical qubits. Several prominent error correction codes have been developed and larger and more complex codes are being developed continuously. However, evaluating the fault-tolerance of these larger codes is becoming exponentially more complicated. While conventional methods of proving and evaluating the fault-tolerance of these circuits have worked thus far, they are soon to be obsolete. The aim of this thesis is to develop a framework that automatically evaluates the fault-tolerance of a quantum error correction circuit across different hardware architectures. The framework works as follows: it takes a noiseless quantum error correction code; injects hardware-realistic noise into it; and evaluates the fault-tolerance of the resulting noisy circuit by estimating its logical error rate through Monte Carlo sampling. For the injection of hardware-realistic noise, this thesis considers noise stemming from five different quantum computing hardware architectures: superconducting qubits, neutral atoms, trapped ions, photonic qubits, and spin qubits. The noise model was constructed by extracting single-qubit gate, two-qubit gate and measurement error fidelities from current experimental literature. The noise model and circuit generation is implemented in Python, circuit representation and noise injection is executed in Stim and decoding and estimating the logical error rate is achieved through PyMatching. The framework is evaluated on the repetition code, the surface code, and the color code; the logical error rate is estimated across all five hardware architectures under the noise model; and the results are discussed in the context of hardware compatibility for the given codes.
System-level resource estimation is a key component of fault-tolerant quantum computing (FTQC) toolchains. Its efficiency depends on how global error tolerance is allocated across logical operations, T-state distillation, and rotation synthesis to minimize physical resource overhead. The commonly used uniform-allocation strategy ignores circuit-specific structure and can overprovision inactive or less critical subsystems, leading to inflated space-time estimates. Prior work aims to address this limitation using supervised models trained on offline-generated datasets. However, this approach incurs additional data-generation costs and limits deployment flexibility. To overcome these drawbacks, we propose a training-free optimization framework that performs derivative-free search directly on the Azure Quantum Resource Estimator (AQRE), enabling instance-specific error budget allocation for previously unseen circuits without requiring offline training data. To evaluate robustness to optimizer choice, we instantiate the framework with two structurally distinct metaheuristics, simulated annealing and quantum particle swarm optimization. We evaluate our framework across 433 circuits spanning 2 to 91 qubits from 31 families in the MQT Bench suite. Across the benchmark suite, both methods reduce space-time cost by more than 33\% on average and agree within 1.34\% points, indicating that the gains are stable across different metaheuristic search strategies. Our analysis further finds that the optimization benefit is driven primarily by error-profile asymmetry rather than circuit scale, and the metric, Gini coefficient of optimized allocation, provides an interpretable diagnostic of expected improvement. Together, these results position adaptive error budget allocation as a system-software optimization layer for FTQC resource estimation pipeline.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit. We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.