Layer codes are three-dimensional local CSS codes of check weight at most six, obtained by quasi-concatenating a CSS input code with unrotated surface code patches. What is established about them describes the code, not the circuit that measures it. In this work, we evaluate them as active memories under circuit-level noise. Doing so first requires a syndrome extraction circuit, and the junction stabilizers that couple the patches rule out borrowing a surface code patch's CNOT schedule. We present a decoder-free scheduler that constrains hook propagation first and compresses depth afterwards, generate circuits for eighteen layer codes across four input codes, and compare them with surface codes of the same distance, simulated and decoded in the same way. The circuits lose no distance to hook errors on [[4,2,2]]-input codes wherever a circuit-distance proof is affordable, and reach a lower logical error rate than those of a general-purpose scheduler for CSS codes at roughly half its CNOT depth per round. Our primary family built from a [[4,2,2]] input code reaches a circuit-level threshold of $5.06(7)\times 10^{-3}$. The layer code outperforms the surface code in terms of idle robustness: at the same distance it tolerates an interval between syndrome extraction rounds 1.7-3.0 times longer than the rotated surface code. This comes at the cost of 1.7-5.0 times more operations per unit time and approximately five times more physical qubits, both per logical qubit. Finally, we model the cost of the beyond-2D cross-plane CNOTs that the construction demands, and find that their speed matters far more than their fidelity.
Layer codes are three-dimensional local CSS codes of check weight at most six, obtained by quasi-concatenating a CSS input code with unrotated surface code patches. What is established about them describes the code, not the circuit that measures it. In this work, we evaluate them as active memories under circuit-level noise. Doing so first requires a syndrome extraction circuit, and the junction stabilizers that couple the patches rule out borrowing a surface code patch's CNOT schedule. We present a decoder-free scheduler that constrains hook propagation first and compresses depth afterwards, generate circuits for eighteen layer codes across four input codes, and compare them with surface codes of the same distance, simulated and decoded in the same way. The circuits lose no distance to hook errors on [[4,2,2]]-input codes wherever a circuit-distance proof is affordable, and reach a lower logical error rate than those of a general-purpose scheduler for CSS codes at roughly half its CNOT depth per round. Our primary family built from a [[4,2,2]] input code reaches a circuit-level threshold of 5.06(7)×10−3. The layer code outperforms the surface code in terms of idle robustness: at the same distance it tolerates an interval between syndrome extraction rounds 1.7-3.0 times longer than the rotated surface code. This comes at the cost of 1.7-5.0 times more operations per unit time and approximately five times more physical qubits, both per logical qubit. Finally, we model the cost of the beyond-2D cross-plane CNOTs that the construction demands, and find that their speed matters far more than their fidelity.
The realization of quantum error correction protocols whose logical error rates are suppressed far below physical error rates relies on an intricate combination: the error-correcting code's efficiency, the syndrome extraction circuit's fault tolerance and overhead, the decoder's quality, and the device's constraints, such as physical qubit count and connectivity. This work makes two contributions towards error-corrected quantum devices. First, we introduce mirror codes, a simple yet flexible construction of LDPC stabilizer codes parameterized by a group G and two subsets of G whose total size bounds the check weight. These codes contain all abelian two-block group algebra codes, such as bivariate bicycle (BB) codes. At the same time, they are manifestly not CSS in general, thus deviating substantially from most prior constructions. Fixing a check weight of 6, we find [[60,4,10]],[[36,6,6]],[[48,8,6]], and [[85,8,9]] codes, all of which are not CSS; we also find several weight-7 codes with kd>n.
Next, we construct syndrome extraction circuits that trade overhead for provable fault tolerance. These circuits use 1-2, 3, and 6 ancillae per check, and respectively are partially fault-tolerant (FT), provably FT on weight-6 CSS codes, and provably FT on \emph{all} weight-6 stabilizer codes. Using our constructions, we perform end-to-end quantum memory experiments on several representative mirror codes under circuit-level noise. We achieve an error pseudothreshold on the order of 0.2%, approximately matching that of the [[144,12,12]] BB code under the same model. These findings position mirror codes as a versatile candidate for fault-tolerant quantum memory, especially on smaller-scale devices in the near term.
Hook errors are a major challenge in implementing logical operations with the surface code, because they can reduce the fault distance below the code distance. This motivates syndrome-extraction circuits that suppress hook-error effects for the stabilizer layouts that appear during logical operations. However, the existing methods either increase circuit depth or require simultaneous execution of measurements and CNOT gates, both of which introduce additional overheads and degrade the threshold. We propose the ZX interleaving syndrome extraction, which preserves the full fault distance d for any surface-code layout with regular stabilizer tiles at minimum depth, i.e., four layers of CNOT gates, without requiring additional circuit depth or simultaneous execution of measurements and CNOT gates. The key idea is to interleave the Z and X stabilizer tiles so that hook-error edges in the decoding graph are shortened and effectively eliminated. Numerical simulations under uniform depolarizing noise for memory and lattice-surgery experiments confirm that the proposed method achieves a full fault distance of d, whereas the best existing minimum-depth approach achieves d−1. Since the full fault distance is achievable for any regular tiling layout of the surface code, the proposed method may serve as an indispensable technique for practical fault-tolerant quantum computation.
Fault-tolerant quantum memories depend on the syndrome extraction circuit as much as on the underlying code. Ancilla-free or dynamic circuits are an effective way to improve this circuit layer. For the 6.6.6 honeycomb Floquet code, making the circuit dynamic raises the threshold and lowers the qubit overhead, but at the cost of halving the spatial code distance. A dynamic construction for the 4.8.8 lattice layout was conjectured to preserve full distance. I confirm this and give a dynamic measurement circuit for the CSS 4.8.8 Floquet code. To benchmark it, I construct and compare four circuit-level implementations on a torus, including two dynamic variants (with and without mid-circuit resets), the standard ancilla-based circuit, and a pipelined ancilla-based circuit. Under circuit-level depolarising noise, the reset dynamic circuit reaches a per-round threshold of 0.463%(0.490%) with MWPM (BP+matching), while the no-reset variant reaches the highest threshold of all four circuits at 0.512%(0.574%). The standard ancilla-based circuit only achieves 0.228%(0.240%), but the pipelined schedule reaches 0.478%(0.489%). The reset dynamic circuit also has a faster-growing timelike distance, with 2≤dt/nqec≤3 asymptotically against a tight 3/2 for the other three, and running it for fewer rounds gives the smallest spacetime volume in the fast-reset regime, while the no-reset variant is smallest in the slow-reset regime. The 4.8.8 dynamic circuits therefore see the expected threshold gain and overhead reduction without the spatial-distance cost, demonstrating the advantage of dynamic syndrome extraction in Floquet codes.
We present a fast and effective framework for analysing and designing syndrome extraction circuits (SECs). Our approach is based on left--right circuits, a general SEC design that maintains low depth and avoids gate interleaving constraints by staggering X and Z stabiliser checks. Initially proposed for specific classes of codes, we generalise this construction to arbitrary CSS codes and optimise the circuit structure to achieve low qubit idling time, large effective distance, and reduced minimum-weight failure mechanisms. A key component of our framework is the formal notion of residual errors and their associated distance metrics, which form lightweight proxies for capturing error propagation and quantifying the potential harm of circuit-level errors. Applying our automated framework to diverse classes of codes, we observe consistent improvements in logical performance of up to an order of magnitude compared to existing single-ancilla SEC designs. Moreover, by directly applying these proxies, we prove that no non-interleaving SEC can achieve circuit distance 12 for the gross code, and we identify an explicit circuit that we conjecture achieves distance 11, exceeding previously known constructions.
In the rotated surface code, hook errors (errors on auxiliary qubits midway through syndrome extraction that propagate to correlated two-qubit data errors) can reduce the circuit-level code distance by a factor of two if the extraction schedule is poorly chosen. The traditional approach uses N-shaped and Z-shaped schedules, selecting the orientation in each plaquette to avoid hook errors aligned with logical operators. However, this becomes increasingly complex within lattice surgery primitives with varied boundary geometries, and requires a 7-step schedule to avoid gate collisions. We propose the diagonal schedule, which orients hook errors along the diagonal of each plaquette. These diagonal errors crucially never align with logical operators regardless of boundary orientation, achieving full code distance. The diagonal schedule is globally uniform: all X-type plaquettes use one schedule and all Z-type plaquettes use another, eliminating geometry-dependent planning. On hardware supporting parallel measurement, reset, and gate operations, the schedule achieves a minimal period of 6 time steps, compared to 7 for the traditional approach. We demonstrate effectiveness for memory experiments, spatial junctions, spatial Hadamard gates, and patch rotation, showing equivalent or improved logical error rates while simplifying circuit construction.
Abstract We present a CSS quantum error correcting code on the Face-Centered Cubic (FCC) lattice that combines surface-code-compatible K=4 connectivity with native inter-sheet logical gates between co-located CSS code blocks — a combination not previously achieved among well-studied codes. The construction has two parts. First, restricting the [[3L³, 2L³+2, 3]] FCC lattice code to a single triad sheet yields the sheet code with parameters [[L³, 2L, L]] at even L (or [[L³, L, L]] as a planar variant), uniform weight-4 stabilizers, and K=4 per-qubit connectivity. Three triad sheets share the FCC lattice geometry and can be deployed in one of three ways — monolithic 2D for small L, a three-layer stacked architecture for scalable deployment, or native 3D hardware — in each case encoding 6L logical qubits at distance L. Second, we introduce a fault-tolerant lattice surgery protocol that uses local FCC triangle measurements to implement joint Pauli measurements between logical qubits in different sheets. Each surgery operation adds O(L) two-qubit gates to the O(L³) per-round syndrome extraction cost. Under circuit-level depolarizing noise with MWPM decoding, the static memory threshold is p_th ≈ 0.63% and the surgery threshold is p_th ≈ 0.5%, both above the operating range of current quantum processors. Compared to surface code lattice surgery (also K=4, lattice surgery confined within a single patch), the sheet code provides 2L logicals per sheet at the same distance and connectivity; compared to bivariate bicycle codes (which target inter-block gates between physically separated modules at K=6 with long-range couplers), the sheet code achieves inter-sheet gates at K=4 with only short-range couplings between co-located sheets.