Manufacturability is one of several constraints on developing solid-state quantum processors, along with qubit performance, control, connectivity, cryogenic operation, and fault tolerance. Chemical residues, structural disorder, and non-uniform interfaces introduced during fabrication can compromise qubit coherence. Two-dimensional (2D) materials, with their atomically thin crystals and van der Waals interfaces, offer routes to address some of these challenges. Their concurrent development as next-generation CMOS channel materials motivates an examination of whether relevant processes can be transferred to quantum chips. This Perspective evaluates the opportunities and limitations of 2D materials for CMOS-compatible quantum hardware.
Manufacturability is one of several constraints on developing solid-state quantum processors, along with qubit performance, control, connectivity, cryogenic operation, and fault tolerance. Chemical residues, structural disorder, and non-uniform interfaces introduced during fabrication can compromise qubit coherence. Two-dimensional (2D) materials, with their atomically thin crystals and van der Waals interfaces, offer routes to address some of these challenges. Their concurrent development as next-generation CMOS channel materials motivates an examination of whether relevant processes can be transferred to quantum chips. This Perspective evaluates the opportunities and limitations of 2D materials for CMOS-compatible quantum hardware.
Abstract Even the quantum simulation of an apparently simple molecule such as Fe2S2requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore’s law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal–oxide–semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal–oxide–semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal–oxide–semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal–oxide–semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal–oxide–semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.
Atomically thin two-dimensional materials, with their ultra-thin structure and exceptional sensitivity to the local environment, are emerging as an important platform for next-generation quantum sensing. Their van der Waals bonding and atomic thin layers allow sensing elements to be placed in extremely close proximity to target systems—often just a few atoms away. This proximity dramatically enhances interactions with local optical, mechanical, and electrostatic fields, enabling exceptionally sensitive detection with ultrahigh spatial resolution. Beyond sensitivity, the layered van der Waals architecture offers a unique opportunity to integrate multiple sensing functions into a unified platform, where sensing, signal amplification, and readout can be distributed across tailored layers rather than relying on a single sensor element. Recent advances in optically addressable spin defects in hexagonal boron nitride and excitonic and polaritonic platforms in transition-metal dichalcogenides highlight the emergence of a new generation of quantum and quantum-enhanced sensors. These sensors conform to various substrates and enable multiparameter detection. In this Perspective, we outline the principles that distinguish atomically thin quantum sensors from bulk counterparts and explore emerging opportunities and challenges in developing scalable, multifunctional 2D quantum sensing technologies.
Quantum computing is transitioning from theoretical development to scalable hardware implementation, yet qubit instability caused by thermal noise, decoherence, electromagnetic interference, and material imperfections remains a central barrier to achieving fault-tolerant quantum processing. Cryogenic materials and ultra-low noise environments have emerged as foundational requirements in stabilizing qubit operation, prolonging coherence time, and enabling quantum error correction for large-scale computational reliability. This paper investigates critical advancements in cryogenic superconductors, magnetic-shielding architectures, dilution refrigeration systems, noise-suppressed signal routing, phonon-limited material engineering, and quantum-grade chip fabrication. Through experimental and simulated benchmarking, we analyze coherence improvements, qubit lifetimes, fabrication tolerances, and environmental noise thresholds necessary for fault-tolerant operation. Data findings confirm that next-generation cryogenic material stacks reduce qubit error rates by 83%, increase coherence time >500 μs in transmon qubits, and support quantum error correction thresholds for practical scalability. The study provides a roadmap for manufacturing stable quantum hardware through material purity innovations, thermal isolation architectures, and cryogenic noise-management frameworks.
Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.
Quantum information science is entering a second phase, the Quantum Evolution 2.0, in which the challenge has shifted from demonstrating coherent control of individual quantum states to building scalable multi-qubit processors and networks. This transition places materials science at the center of the field. Across superconducting circuits, quantum defects, quantum photonic devices, and emerging materials platforms, including two-dimensional materials and heterostructures, performance is now limited less by device design than by poorly controlled surfaces, buried interfaces, and defects whose atomic identities remain incompletely known. This review surveys the materials challenges of these quantum platforms together with the characterization methods needed to resolve them. For each platform we identify the dominant decoherence mechanisms, the current state of materials understanding, and the most pressing open materials problems. A cross-platform comparison then reveals a shared structure-coherence problem. The implicated material chemistry recurs across platforms, involving light elements in disordered or buried environments, yet no platform can quantitatively connect a specific atomic-scale structure to a measured change in coherence. We close by identifying three needs, mechanistic understanding of decoherence at the atomistic level, high-throughput proxy metrics predictive of device performance, and characterization tools built for quantum materials, whose resolution would advance coherence, scalability, and integration across all platforms.
The convergence of quantum computing and VLSI technology represents a promising yet challenging direction for next-generation computing systems. This chapter examines the fundamental challenges involved in integrating quantum computing principles with established VLSI design methodologies. Key issues such as device scalability, fabrication variability, error rates, cryogenic operation, and interfacing quantum hardware with classical CMOS control and readout circuits are discussed. The chapter also explores how VLSI techniques contribute to the development of scalable quantum systems through advanced fabrication processes, compact control electronics, and system-level integration strategies. Emphasis is placed on hybrid quantum–classical architectures, where VLSI plays a crucial role in enabling efficient control, error correction, and data processing. By analyzing both technological constraints and emerging solutions, this chapter highlights the opportunities arising from the convergence of quantum computing and VLSI, providing insight into the future of high-performance and unconventional computing platforms.