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arXiv:2609.14478

NAQsim: Full-Stack Architecture Simulation Framework for Fast and Space-Efficient Neutral Atom Quantum Computing

Yosuke Ueno, Shinichi Sunami, Toshihide Hinokuma, Yasunari Suzuki, Akihisa Goban, Hayata Yamasaki, Teruo Tanimoto, Ilkwon Byun

quant-phcs.ARSubmitted Sep 13, 2026• Announced Sep 15, 2026• 0 citations
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Abstract

Technological advances in neutral-atom platforms have opened a new path toward designing efficient protocols for fault-tolerant quantum computing (FTQC). However, each physical operation is still orders of magnitude slower than on other platforms, such as superconducting qubits. Therefore, architects must identify fast and efficient FTQC architectures, which require reliable modeling tools to explore various design choices across the software, classical hardware, and quantum device stacks of neutral-atom platforms. In this paper, we propose NAQsim, an open-source simulation framework for neutral-atom FTQC architectures based on transversal gates. As its key feature, NAQsim enables detailed full-stack architecture evaluation that opens opportunities to explore previously overlooked performance bottlenecks. As a first use case for NAQsim, we identify one such bottleneck, patch rotations, perform full-stack co-optimization, and finally derive a near-rotation-free architecture (D3-ROT). For practical FTQC benchmark workloads, D3-ROT achieves a 2.27x speedup from this single bottleneck alone, with minimal footprint overhead. These results point to a much broader space of full-stack optimizations that NAQsim makes accessible for transversal surface-code architectures and beyond.

Comments
18 pages, 20 figures, 4 tables. Accepted to the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026)

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Technological advances in neutral-atom platforms have opened a new path toward designing efficient protocols for fault-tolerant quantum computing (FTQC). However, each physical operation is still orders of magnitude slower than on other platforms, such as superconducting qubits. Therefore, architects must identify fast and efficient FTQC architectures, which require reliable modeling tools to explore various design choices across the software, classical hardware, and quantum device stacks of neutral-atom platforms.
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Neutral-atom arrays are a leading qubit technology for large-scale, fault-tolerant quantum computing (FTQC). A dominant error source on this platform is qubit loss, which accrues with every operation and movement. The presence of loss undermines the promises of existing architectural work. Standard error correction targets stochastic Pauli errors and cannot correct loss, so most FTQC performance analyses are not directly compatible with it. Moreover, compilation and routing decisions, which strongly affect overall loss, are typically optimized against Pauli-error cost models and often remain loss-agnostic, potentially increasing exposure to the loss channel. In this work, we comprehensively model the effect of qubit loss on neutral-atom FTQC and develop a loss-tolerant transversal-gate architecture. We treat loss not as a predetermined error parameter but as a dynamic budget spent across a whole program, allowing us to control it by co-designing layout, compilation, and decoding. We target a physical implementation with no separate storage and entangling zones, eliminating the repeated SLM-AOD handoffs and long-distance shuttling that dominate loss in other layouts. We develop compiler optimizations that maximize gate parallelism while respecting the RF tone budget and AOD bandwidth constraints. Our work couples these with a loss-aware, delayed-erasure decoder and an end-to-end loss-aware magic state cultivation protocol. Overall, we improve accumulated loss per syndrome-extraction round by up to 2.15X against a zoned baseline and reduce logical error rates by over two orders of magnitude versus current architectures. Our framework also informs concrete device targets such as continuous reloading rates, AOD counts, and shuttling trajectory choices. We expect these insights to matter for system architects as neutral-atom hardware scales.
Quantum computing experiments have made remarkable progress in demonstrating key components of error-corrected quantum computing, a prerequisite for scalable quantum computation. While we anticipate the near-term arrival of early fault-tolerant quantum hardware capable of a million reliable quantum operations, the cost of preparing low-noise “magic resource states,” which are necessary for performing universal quantum computation, presents a formidable challenge. The recently proposed partially fault-tolerant architecture based on a space-time efficient analog rotation (STAR) approach attempts to address this challenge by using postselection to prepare low-noise, arbitrary small-angle magic states. Its proposed physical implementation, however, assumes fixed qubit connectivity, resulting in implementation costs closer to leading fully fault-tolerant approaches. In this work, we propose the transversal STAR architecture and co-design it with neutral-atom quantum hardware, deriving explicit and significant savings in logical layout, time, and space overhead. Through detailed circuit-level simulations, we derive the logical noise model for surface-code-based transversal STAR gadgets and verify their composability. At its limit, the transversal STAR architecture with neutral atoms can efficiently simulate local Hamiltonians with a total simulation volume exceeding 600, defined as the product of the number of logical qubits and Hamiltonian evolution timescales. Achieving this limit would require approximately 10 000 physical qubits at a physical error rate of 10 − 3 . This is equivalent to a fully fault-tolerant computation requiring over 10 6 – 10 7 T gates and a potential > 100 × saving on space-time volume for equivalent simulation over current, state-of-the-art protocols. Finally, we extend the transversal STAR architecture to high-rate quantum low-density parity-check codes, demonstrating how a limited set of highly parallel transversal Clifford gates and generalized small-angle magic injection can be utilized for effective quantum simulation. We anticipate that the co-designed transversal STAR architecture could substantially reduce the physical resources necessary for early fault-tolerant quantum simulation at the megaquop scale.
The transition to the fault-tolerant era exposes the limitations of homogeneous quantum systems, where no single qubit modality simultaneously offers optimal operation speed, connectivity, and scalability. In this work, we propose a strategic approach to Heterogeneous Quantum Architectures (HQA) that synthesizes the distinct advantages of the superconducting (SC) and neutral atom (NA) platforms. We explore two architectural role assignment strategies based on hardware characteristics: (1) We offload the latency-critical Magic State Factory (MSF) to fast SC devices while performing computation on scalable NA arrays, a design we term MagicAcc, which effectively mitigates the resource-preparation bottleneck. (2) We explore a Memory-Compute Separation (MCSep) paradigm that utilizes NA arrays for high-density qLDPC memory storage and SC devices for fast surface-code processing. Our evaluation, based on a comprehensive end-to-end cost model, demonstrates that principled heterogeneity yields significant performance gains. Specifically, our designs achieve 752×752\times752× speedup over NA-only baselines on average and reduce the physical qubit footprint by over 10×10\times10× compared to SC-only systems. These results chart a clear pathway for leveraging cross-modality interconnects to optimize the space-time efficiency of future fault-tolerant quantum computers.
Efficient quantum error correction and fault-tolerant quantum computing require scalable, high-fidelity long-range connectivity. In neutral-atom quantum computers, this is commonly achieved through atom transport, but shuttling introduces latency and motional heating that worsen with system size. Here, we introduce a neutral-atom architecture based on static atomic buses, in which auxiliary mediator atoms enable long-range entangling operations without qubit transport. The architecture naturally supports long-range stabilizer measurements in high-rate LDPC codes and transversal logical gates between neighboring surface-code patches, enabling a modular framework for efficient logical memories, Clifford computation, and magic-state distillation. To realize these capabilities, we co-design optimal-control protocols for bus-mediated controlled-Z gates that incorporate both microscopic neutral-atom dynamics and architectural constraints. We obtain smooth bus-mediated gates with fidelities approaching 99.9% and durations of a few hundred nanoseconds by combining time-optimal control with interaction-flatness and robustness constraints. Large-scale simulations of quantum error correction and logical entangling operations between neighboring surface-code patches predict more than an order-of-magnitude improvement in logical error rates compared with atom-shuttling architectures under realistic noise. The architecture achieves logical gate times of approximately 100 us and quantum-error-correction cycle times of about 1 ms for code distances d<12. These results establish static atomic buses as a practical alternative to atom shuttling for scalable fault-tolerant neutral-atom quantum computing.
Neutral atom quantum computers (NAQCs) have emerged as promising candidates for scalable quantum computing, thanks to their advanced hardware capabilities, particularly qubit movement and the Zoned Architecture (ZA). However, fully harnessing these features presents significant compilation challenges, requiring careful coordination across gate scheduling, qubit positioning, atom movement, and inter-zone communication. In this paper, we propose PowerMove, an efficient compiler for NAQCs that unlocks new optimization opportunities, significantly improving qubit movement strategies while seamlessly integrating ZA. Our evaluation demonstrates orders-of-magnitude fidelity improvements over state-of-the-art methods, with execution time reduced by up to 3.76× and compilation time accelerated by up to 216.9× across various NISQ applications. Furthermore, PowerMove extends naturally to the fault-tolerant quantum computing (FTQC) setting, where physical qubits are replaced by logical qubits encoded in QEC codes, achieving a 4.78× reduction in execution time. These results highlight PowerMove's impact on both near-term NISQ applications and long-term FTQC implementations. We have open-sourced our codes at https://github.com/Scarlett0815/PowerMove to facilitate further research and collaboration within the community.