Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2609.09980

Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems

Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto, Patrick Hopf, Deborah Volpe, Helmut Seidl, Giovanna Turvani, Robert Wille, Christian B. Mendl, Martin Schulz

quant-phcs.AIcs.ETSubmitted Sep 9, 2026• Announced Sep 10, 2026• 0 citations
v1 · Sep 9, 2026v2 · Sep 15, 2026
arXivHTMLPDF

Abstract

High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.

Comments
Accepted at the 2nd International Workshop for Software Frameworks and Workload Management on Quantum and HPC Ecosystems (SFWM), co-located with SC26

Related papers

Fidelity-Based Quantum Device Selection Using Graph Neural Networks

Antonio Tudisco, Patrick Hopf, Linus Schulte +3 more

Modern High-Performance Computing (HPC) infrastructures are increasingly integrating multiple Quantum Processing Units (QPUs) of different types alongside classical resources. Unlike traditional accelerator scheduling, quantum device selection affects not only performance but also the quality of the computed result because current quantum hardware exhibits device-dependent noise characteristics. This makes efficient and fidelity-based device selection a key challenge in multi-QPU environments. In this work, we propose a Graph Neural Network (GNN) model that exploits the structural representation of quantum circuits to predict their execution fidelity across different QPUs. By operating on uncompiled circuits, the approach supports earlystage device selection and enables making informed scheduling decisions. We evaluate the model on a diverse set of benchmark circuits compiled for superconducting and trapped-ion devices. The results show that the proposed approach outperforms existing baseline models, achieving 30% Mean Squared Error (MSE) and 20% Mean Absolute Error (MAE) reduction, and provides an effective basis for fidelity-based scheduling in heterogeneous HPC-quantum systems.

IEEE International Conference on Quantum Software (QSW)•Jul 1, 2026•0 citations

Towards multi-QPU quantum systems: circuit mapping for high execution fidelity and low communication overhead

Longshan Xu, Edwin Sha, Weixuan Liu +1 more

Abstract Multi-quantum processing unit (multi-QPU) architectures have emerged as a promising route for scaling up quantum computing. However, quantum circuit execution across QPUs introduces remote operations, which have lower fidelity than local operations and require additional communication resources. Circuit mapping, which determines where quantum information and operations are placed, critically affects the number of required remote operations and, consequently, the reliability and efficiency of distributed execution. Here, we introduce NAVI, a communication- and noise-aware circuit mapping framework for multi-QPU systems. NAVI addresses three mapping decisions in a staged compiler workflow: how to partition qubits according to evolving interaction patterns, which communication mode should be used for remote operations, and which physical QPUs should host the resulting qubit partitions under heterogeneous noise. Across a diverse set of benchmark circuits, NAVI reduces cumulative execution error by 40% to 55% and communication resource consumption by 60% to 72% on average compared with existing methods.

Quantum Science and Technology•Oct 13, 2026•0 citations

Graph Neural Network-Based Predictor for Optimal Quantum Hardware Selection

Antonio Tudisco, Deborah Volpe, Giacomo Orlandi +1 more

The growing variety of quantum hardware technologies, each with unique peculiarities such as connectivity and native gate sets, creates challenges when selecting the best platform for executing a specific quantum circuit. This selection process usually involves a brute-force approach: compiling the circuit on various devices and evaluating performance based on factors such as circuit depth and gate fidelity. However, this method is computationally expensive and does not scale well as the number of available quantum processors increases. In this work, we propose a Graph Neural Network (GNN)based predictor that automates hardware selection by analyzing the Directed Acyclic Graph (DAG) representation of a quantum circuit. Our study evaluates 498 quantum circuits (up to 27 qubits) from the MQT Bench dataset, compiled using Qiskit on four devices: three superconducting quantum processors (IBM-Kyiv, IBM-Brisbane, IBM-Sherbrooke) and one trappedion processor (IONQ-Forte). Performance is estimated using a metric that integrates circuit depth and gate fidelity, resulting in a dataset where 93 circuits are optimally compiled on the trappedion device, while the remaining circuits prefer superconducting platforms. By exploiting graph-based machine learning, our approach avoids extracting the circuit features for the model evaluation but directly embeds it as a graph, significantly accelerating the optimal target decision-making process and maintaining all the information. Experimental results prove$\mathbf{9 4. 4 \%}$accuracy and an$\mathbf{8 5. 5 \%}$F1 score for the minority class, effectively predicting the best compilation target. The developed code is publicly available on GitHub (https://github.com/antotu/GNN-Model-Quantum-Predictor).

arXiv:2507.19093•IEEE International Conference on Quantum Computing and Engineering (QCE)•Aug 30, 2025•1 citation

Parallel Circuit Execution for Scalable Quantum Computation

Avimita Chatterjee, W. Michael Brown, Siyuan Niu +2 more

Today's quantum processors have tens to hundreds of physical qubits, but reliable execution of arbitrary circuits remains limited to fewer than 30 entangled qubits across hardware modalities. Building upon prior work, we introduce an error- and topology-aware method for mapping multiple independent circuits onto disjoint regions of a single large-scale QPU for parallel circuit execution. For applications with many similarly sized circuits, such as observable estimation for Hamiltonian simulation, this approach can reduce billed QPU execution time, with ideal speedup proportional to the number of usable partitions. We demonstrate the approach on IBM's 156-qubit ibm_boston processor using standard QED-C benchmark and Hamiltonian-based observable-estimation workloads. Compared with standard sequential execution, parallel execution reduces billed execution time by 3.5-5.5x while retaining 83-92% of the sequential fidelity. We further evaluate the scaling of parallel circuit execution using GPU-accelerated classical simulation, distributing measurement circuits across GPUs via MPI. Using CUDA-Q on the NERSC Perlmutter system, we achieve up to 13.8x speedup on 16 GPUs (86% parallel efficiency) for an H2 electronic-structure simulation, with scaling evaluated across multiple Hamiltonians and circuit counts. These results provide an indication of the performance ceiling that parallel execution on future quantum hardware may eventually approach. Both execution modes are implemented as a runtime option within the QED-C Application-Oriented Benchmark suite. Together, the results show that circuit-level parallelism can reduce execution cost on current quantum hardware and simulation time on GPU clusters, with the potential for greater benefits as device quality and qubit counts increase.

quant-pharXiv:2609.12172•Sep 14, 2026•0 citations

Adaptive Job Scheduling in Quantum Clouds Using Reinforcement Learning

Waylon Luo, Jiapeng Zhao, Tong Zhan +1 more

Present-day quantum systems face critical bottlenecks, including limited qubit counts, brief coherence intervals, and high susceptibility to errors—all of which obstruct the execution of large and complex circuits. The advancement of quantum algorithms has outpaced the capabilities of existing quantum hardware, making it difficult to scale computations effectively. Additionally, inconsistencies in hardware performance and pervasive quantum noise undermine system stability and computational accuracy. To optimize quantum workloads under these constraints, strategic approaches to task scheduling and resource coordination are essential. One of the persistent challenges in this domain is how to efficiently divide and execute large circuits across multiple quantum processors (QPUs), especially in error-prone environments. In response, we introduce a simulation-based tool that supports distributed scheduling and concurrent execution of quantum jobs on networked QPUs connected via real-time classical channels. The tool models circuit decomposition for workloads that surpass individual QPU limits, allowing for parallel execution through inter-processor communication. Using this simulation environment, we compare four distinct scheduling techniques—among them, a model informed by reinforcement learning. These strategies are evaluated across multiple metrics, including runtime efficiency, fidelity preservation, and communication costs. Our analysis underscores the trade-offs inherent in each approach and highlights how parallelized, noise-aware scheduling can meaningfully improve computational throughput in distributed quantum infrastructures.

arXiv:2506.10889•Proceedings of the International Conference on Parallel Processing•Sep 8, 2025•5 citations

Architecture-driven compiler optimisations for scalable quantum computing systems

Xiangyu Ren

Scalable quantum computing requires execution models that go beyond the capacity of a single quantum processing unit (QPU). Although current hardware platforms continue to increase in qubit count, large fault-tolerant applications require substantially more physical qubits, stronger connectivity, and lower effective error rates than a monolithic near-term device can provide. Multi-QPU and multi-core architectures therefore form an important route towards larger quantum systems. However, distributing a quantum computation introduces compiler and architecture constraints that do not arise in conventional classical distribution. A partitioned quantum circuit separates gates and qubits that may still be logically entangled or mutually dependent. The system must therefore provide quantum resources that support entanglement between the distributed circuit fragments, while each local subcircuit must remain executable on the hardware topology of its assigned QPU. In this thesis, graph states serve as the explicit interconnection resources for these nonlocal dependences: they encode the entanglement structure required to support teleportation-based operations across QPUs. This thesis studies scalable quantum execution as an architecture-driven compilation problem. It develops a staged framework in which distribution, graph-state-based interconnection, and interconnection robustness are treated as dependent compiler decisions. The framework addresses three connected questions: 1) how a large quantum circuit should be divided when the resulting subcircuits must match real QPU topologies; 2) how the graph states required to entangle and operate across the distributed circuit boundaries can be prepared efficiently on constrained hardware; and 3) how those graph-state resources can remain useful under the loss and fusion failures that arise during preparation and use. These questions define an execution path from a large logical circuit to distributed local workloads connected by explicit entanglement resources. The thesis makes three main technical contributions that instantiate this framework. 1) It introduces hardware-aware circuit cutting, which incorporates the relationship between subcircuit interaction graphs and target QPU topology into the partitioning objective. This stage produces distributed workloads and explicit cut boundaries where quantum entanglement must be supplied across QPUs. 2) It formulates graph-state preparation as the resource-generation stage for those boundaries and develops methods that reduce preparation depth and emitter usage by exploiting graph-state equivalence and divide-and-conquer construction. 3) It develops a robust graph-state interconnection scheme that uses tree-encoded fusion and spin-memory-assisted compilation to tolerate photon loss and probabilistic fusion failures, so that the graph state can serve as a reliable connection between distributed quantum program fragments.

•Aug 12, 2026•0 citations
High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.
Modern High-Performance Computing (HPC) infrastructures are increasingly integrating multiple Quantum Processing Units (QPUs) of different types alongside classical resources. Unlike traditional accelerator scheduling, quantum device selection affects not only performance but also the quality of the computed result because current quantum hardware exhibits device-dependent noise characteristics. This makes efficient and fidelity-based device selection a key challenge in multi-QPU environments. In this work, we propose a Graph Neural Network (GNN) model that exploits the structural representation of quantum circuits to predict their execution fidelity across different QPUs. By operating on uncompiled circuits, the approach supports earlystage device selection and enables making informed scheduling decisions. We evaluate the model on a diverse set of benchmark circuits compiled for superconducting and trapped-ion devices. The results show that the proposed approach outperforms existing baseline models, achieving 30% Mean Squared Error (MSE) and 20% Mean Absolute Error (MAE) reduction, and provides an effective basis for fidelity-based scheduling in heterogeneous HPC-quantum systems.
Abstract Multi-quantum processing unit (multi-QPU) architectures have emerged as a promising route for scaling up quantum computing. However, quantum circuit execution across QPUs introduces remote operations, which have lower fidelity than local operations and require additional communication resources. Circuit mapping, which determines where quantum information and operations are placed, critically affects the number of required remote operations and, consequently, the reliability and efficiency of distributed execution. Here, we introduce NAVI, a communication- and noise-aware circuit mapping framework for multi-QPU systems. NAVI addresses three mapping decisions in a staged compiler workflow: how to partition qubits according to evolving interaction patterns, which communication mode should be used for remote operations, and which physical QPUs should host the resulting qubit partitions under heterogeneous noise. Across a diverse set of benchmark circuits, NAVI reduces cumulative execution error by 40% to 55% and communication resource consumption by 60% to 72% on average compared with existing methods.
The growing variety of quantum hardware technologies, each with unique peculiarities such as connectivity and native gate sets, creates challenges when selecting the best platform for executing a specific quantum circuit. This selection process usually involves a brute-force approach: compiling the circuit on various devices and evaluating performance based on factors such as circuit depth and gate fidelity. However, this method is computationally expensive and does not scale well as the number of available quantum processors increases. In this work, we propose a Graph Neural Network (GNN)based predictor that automates hardware selection by analyzing the Directed Acyclic Graph (DAG) representation of a quantum circuit. Our study evaluates 498 quantum circuits (up to 27 qubits) from the MQT Bench dataset, compiled using Qiskit on four devices: three superconducting quantum processors (IBM-Kyiv, IBM-Brisbane, IBM-Sherbrooke) and one trappedion processor (IONQ-Forte). Performance is estimated using a metric that integrates circuit depth and gate fidelity, resulting in a dataset where 93 circuits are optimally compiled on the trappedion device, while the remaining circuits prefer superconducting platforms. By exploiting graph-based machine learning, our approach avoids extracting the circuit features for the model evaluation but directly embeds it as a graph, significantly accelerating the optimal target decision-making process and maintaining all the information. Experimental results prove94.4%\mathbf{9 4. 4 \%}94.4%accuracy and an85.5%\mathbf{8 5. 5 \%}85.5%F1 score for the minority class, effectively predicting the best compilation target. The developed code is publicly available on GitHub (https://github.com/antotu/GNN-Model-Quantum-Predictor).
Today's quantum processors have tens to hundreds of physical qubits, but reliable execution of arbitrary circuits remains limited to fewer than 30 entangled qubits across hardware modalities. Building upon prior work, we introduce an error- and topology-aware method for mapping multiple independent circuits onto disjoint regions of a single large-scale QPU for parallel circuit execution. For applications with many similarly sized circuits, such as observable estimation for Hamiltonian simulation, this approach can reduce billed QPU execution time, with ideal speedup proportional to the number of usable partitions. We demonstrate the approach on IBM's 156-qubit ibm_boston processor using standard QED-C benchmark and Hamiltonian-based observable-estimation workloads. Compared with standard sequential execution, parallel execution reduces billed execution time by 3.5-5.5x while retaining 83-92% of the sequential fidelity. We further evaluate the scaling of parallel circuit execution using GPU-accelerated classical simulation, distributing measurement circuits across GPUs via MPI. Using CUDA-Q on the NERSC Perlmutter system, we achieve up to 13.8x speedup on 16 GPUs (86% parallel efficiency) for an H2 electronic-structure simulation, with scaling evaluated across multiple Hamiltonians and circuit counts. These results provide an indication of the performance ceiling that parallel execution on future quantum hardware may eventually approach. Both execution modes are implemented as a runtime option within the QED-C Application-Oriented Benchmark suite. Together, the results show that circuit-level parallelism can reduce execution cost on current quantum hardware and simulation time on GPU clusters, with the potential for greater benefits as device quality and qubit counts increase.
Present-day quantum systems face critical bottlenecks, including limited qubit counts, brief coherence intervals, and high susceptibility to errors—all of which obstruct the execution of large and complex circuits. The advancement of quantum algorithms has outpaced the capabilities of existing quantum hardware, making it difficult to scale computations effectively. Additionally, inconsistencies in hardware performance and pervasive quantum noise undermine system stability and computational accuracy. To optimize quantum workloads under these constraints, strategic approaches to task scheduling and resource coordination are essential. One of the persistent challenges in this domain is how to efficiently divide and execute large circuits across multiple quantum processors (QPUs), especially in error-prone environments. In response, we introduce a simulation-based tool that supports distributed scheduling and concurrent execution of quantum jobs on networked QPUs connected via real-time classical channels. The tool models circuit decomposition for workloads that surpass individual QPU limits, allowing for parallel execution through inter-processor communication. Using this simulation environment, we compare four distinct scheduling techniques—among them, a model informed by reinforcement learning. These strategies are evaluated across multiple metrics, including runtime efficiency, fidelity preservation, and communication costs. Our analysis underscores the trade-offs inherent in each approach and highlights how parallelized, noise-aware scheduling can meaningfully improve computational throughput in distributed quantum infrastructures.
Scalable quantum computing requires execution models that go beyond the capacity of a single quantum processing unit (QPU). Although current hardware platforms continue to increase in qubit count, large fault-tolerant applications require substantially more physical qubits, stronger connectivity, and lower effective error rates than a monolithic near-term device can provide. Multi-QPU and multi-core architectures therefore form an important route towards larger quantum systems. However, distributing a quantum computation introduces compiler and architecture constraints that do not arise in conventional classical distribution. A partitioned quantum circuit separates gates and qubits that may still be logically entangled or mutually dependent. The system must therefore provide quantum resources that support entanglement between the distributed circuit fragments, while each local subcircuit must remain executable on the hardware topology of its assigned QPU. In this thesis, graph states serve as the explicit interconnection resources for these nonlocal dependences: they encode the entanglement structure required to support teleportation-based operations across QPUs. This thesis studies scalable quantum execution as an architecture-driven compilation problem. It develops a staged framework in which distribution, graph-state-based interconnection, and interconnection robustness are treated as dependent compiler decisions. The framework addresses three connected questions: 1) how a large quantum circuit should be divided when the resulting subcircuits must match real QPU topologies; 2) how the graph states required to entangle and operate across the distributed circuit boundaries can be prepared efficiently on constrained hardware; and 3) how those graph-state resources can remain useful under the loss and fusion failures that arise during preparation and use. These questions define an execution path from a large logical circuit to distributed local workloads connected by explicit entanglement resources. The thesis makes three main technical contributions that instantiate this framework. 1) It introduces hardware-aware circuit cutting, which incorporates the relationship between subcircuit interaction graphs and target QPU topology into the partitioning objective. This stage produces distributed workloads and explicit cut boundaries where quantum entanglement must be supplied across QPUs. 2) It formulates graph-state preparation as the resource-generation stage for those boundaries and develops methods that reduce preparation depth and emitter usage by exploiting graph-state equivalence and divide-and-conquer construction. 3) It develops a robust graph-state interconnection scheme that uses tree-encoded fusion and spin-memory-assisted compilation to tolerate photon loss and probabilistic fusion failures, so that the graph state can serve as a reliable connection between distributed quantum program fragments.