Quantum error correction (QEC) codes can correct twice as many erasure errors as Pauli errors. Because of this scaling advantage, there is significant interest in developing qubits whose dominant error channel can be converted into erasures via mid-circuit erasure checks. However, such erasure checks come with hardware overhead in practice. End-of-the-line three-state readout, in which one simultaneously measures a qubit's erasure status and computational state, is an alternative to mid-circuit erasure checks that is generally simpler to implement. In this work, we systematically study the conditions required to enable erasure performance---the doubled error-correction capacity---in the surface code with and without mid-circuit erasure checks. We introduce the moonwalking surface code, the time-reversal of the walking surface code, as a zero-overhead circuit with superior handling of leakage and erasure. Specifically, we show that it enables erasure-like logical error rate scaling when combined with three-state measurement if leaked qubits cause two-qubit gates to be skipped and an appropriate decoder is used. Our decoder, based on a branch-and-bound algorithm, specifically incorporates the noise structure of the skip-gate leaked-qubit effect.
Comments
10 pages main text (5 figures), 9 pages appendix. See also separate Supplementary Materials. v2: added missing funding acknowledgement. v3: updated results after fixing bug in simulation code. Minimal effect
Quantum error correction (QEC) codes can correct twice as many erasure errors as Pauli errors. Because of this scaling advantage, there is significant interest in developing qubits whose dominant error channel can be converted into erasures via mid-circuit erasure checks. However, such erasure checks come with hardware overhead in practice. End-of-the-line three-state readout, in which one simultaneously measures a qubit's erasure status and computational state, is an alternative to mid-circuit erasure checks that is generally simpler to implement. In this work, we systematically study the conditions required to enable erasure performance---the doubled error-correction capacity---in the surface code with and without mid-circuit erasure checks. We introduce the moonwalking surface code, the time-reversal of the walking surface code, as a zero-overhead circuit with superior handling of leakage and erasure. Specifically, we show that it enables erasure-like logical error rate scaling when combined with three-state measurement if leaked qubits cause two-qubit gates to be skipped and an appropriate decoder is used. Our decoder, based on a branch-and-bound algorithm, specifically incorporates the noise structure of the skip-gate leaked-qubit effect.
Erasure qubits offer a promising avenue toward reducing the overhead of quantum error correction (QEC) protocols. However, they require additional operations, such as erasure checks, that may add extra noise and increase the run-time of QEC protocols. To assess the benefits provided by erasure qubits, we focus on the performance of the surface code as a quantum memory. In particular, we analyze various erasure check schedules, find the correctable regions in the phase space of error parameters, and probe the subthreshold scaling of the logical error rate. We then consider a realization of erasure qubits in the superconducting hardware architectures via dual-rail qubits. We use the standard transmon-based implementation of the surface code as the performance benchmark. Our results indicate that QEC protocols with erasure qubits can outperform the ones with state-of-the-art transmons, even in the absence of precise information about the locations of erasure errors.
Recently, significant effort has been devoted towards designing erasure qubits in which dominant physical noise excites detectable leakage states that can be returned to the qubit subspace. Interest in these erasure qubits has been driven by studies showing that the requirements for fault-tolerant quantum error correction are significantly relaxed when noise in every gate operation is dominated by erasures. However, these studies assume perfectly accurate erasure checks after every gate operation which generally come with undesirable time and hardware overhead costs. In this work, we investigate the consequences of using an imperfect but overhead-efficient erasure check for fault-tolerant quantum error correction with the surface code. We show that, under physically reasonable assumptions on the imperfect erasure checks, the threshold error rate is still at least over twice that for Pauli noise. We also study the impact of imperfect erasure checks on the effective error distance and find that it degrades the effective distance under a general error model in which a qubit suffers from depolarizing noise when interacting with a leaked qubit. We then identify a more restrictive but realistic noise model for a qubit that interacts with a leaked qubit, under which the effective error distance is twice that for Pauli noise. We apply our analysis to recently proposed superconducting dual-rail erasure qubits and show that achieving good-performance surface code quantum memories with relaxed system requirements is possible.
Erasure qubits reduce overhead in fault-tolerant quantum error correction (QEC) by converting dominant faults into detectable errors known as erasures. They have demonstrated notable improvements in thresholds and scaling in surface and Floquet code memories. In this work, we use erasure qubits on Bivariate Bicycle (BB) codes from the quantum low-density parity-check (QLDPC) regime. Owing to their sparse structure and favorable rate-distance trade-offs, BB codes are practical candidates for QEC. We introduce BiBiEQ, a novel framework that compiles a given BB code into an erasure-aware memory circuit C_E. This erasure circuit C_E comprises erasure checks (ECs), resets, and erasures spread over a user-specified erasure check schedule (2EC, 4EC). BiBiEQ converts this erasure circuit C_E into the stabilizer circuit C for general-purpose decoding. BiBiEQ provides two engines for this conversion, BiBiEQ-Exact and BiBiEQ-Approx. BiBiEQ-Exact preserves the joint-erasure correlations and serves as our accuracy benchmark, while BiBiEQ-Approx uses an independence approximation to accelerate large sweeps and expose accuracy-throughput trade-offs. Using BiBiEQ, we decode the stabilizer circuits to get a per-round logical error rate (LER) for the BB codes and quantify the effect of the EC schedules on the correctable operating region below the pseudo-threshold. The 4EC schedule keeps the accuracy of both engines close to one another, making BiBiEQ-Approx a reliable proxy for BiBiEQ-Exact for faster sweeps. Below the pseudo-threshold, the code distance (d) hop from distance (d) 6 to 10 yields a drop in LER by 10-17x larger than distance (d) 10 to 12, showing that most gains are realized by d=10.
A remarkable characteristic of quantum computing is the potential for reliable computation despite faulty qubits. This can be achieved through quantum error correction, which is typically implemented by repeatedly applying static syndrome checks, permitting correction of logical information. Recently, the development of time-dynamic approaches to error correction has enabled different codes and implementations that do not rely on static syndrome measurements. Here we experimentally demonstrate three time-dynamic implementations of the surface code, each offering a distinct solution to hardware design challenges faced by surface code realizations. First, we embed the surface code on a hexagonal lattice, reducing the necessary couplings per qubit from four to three. Second, we walk a surface code, swapping the role of data and measure qubits each round, achieving error correction with built-in removal of accumulated non-computational errors. Finally, we realize the surface code using iSWAP gates instead of the traditional CNOT, extending the set of viable gates for error correction without additional overhead. We measure the error suppression factor when scaling from distance-3 to distance-5 codes of Λ35,hex = 2.15(2), Λ35,walk = 1.69(6) and Λ35,iSWAP = 1.56(2), achieving state-of-the-art error suppression for each. Our work demonstrates that dynamic circuit approaches meet the demands for fault tolerance and enable alternative strategies for scalable hardware design. Typical quantum error correcting codes assign fixed roles to the underlying physical qubits. Now the performance benefits of alternative, dynamic error correction schemes have been demonstrated on a superconducting quantum processor.
Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states ∣0L⟩ and ∣1L⟩ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit T1 lifetime exceeding 500μs, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the T1 time of the transmon physical qubit. Coherence times beyond 300μs are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of 10−4. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.
Quantum error correction (QEC) represents a critical enabler for fault-tolerant quantum computing, protecting fragile quantum states from decoherence and operational errors. This paper provides a comprehensive analysis of leading quantum error correction schemes, focusing on surface codes and topological codes within the context of Noisy Intermediate-Scale Quantum (NISQ) era processors. We examine the theoretical foundations of stabilizer codes, compare surface code implementations with code distances ranging from d=3 to d=17, and analyze topological codes including toric codes and color codes. Our investigation encompasses syndrome extraction circuits, logical qubit encoding strategies, and threshold analysis for contemporary quantum hardware platforms. Performance metrics reveal that surface codes achieve error thresholds of approximately 1% with realistic noise models, while topological codes offer architectural advantages for specific qubit connectivity constraints. We discuss implementation challenges on current NISQ processors including IBM Quantum, Google Sycamore, and IonQ systems, addressing qubit overhead, gate fidelity requirements, and decoding algorithms. This analysis provides insights for selecting appropriate error correction schemes based on application requirements and hardware capabilities.