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arXiv:2607.27123

Hardware-efficient erasure-error detection with an integer fluxonium

Junyoung An, Helin Zhang, Jeffrey M. Gertler, Kate Azar, Renée DePencier Piñero, Michael Gingras, Junghyun Kim, Bethany M. Niedzielski, Ilan T. Rosen, Mollie E. Schwartz, Joel Î-j. Wang, Terry P. Orlando, Jeffrey A. Grover, Max Hays, Kyle Serniak, William D. Oliver

quant-phSubmitted Jul 29, 2026• Announced Jul 30, 2026• 0 citations
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Abstract

Erasure-error detection can improve the efficiency of quantum error correction by revealing the times and locations of their error events. In this work, we demonstrate erasure conversions and mid-circuit erasure detections in a single integer fluxonium, in which the states $\mathrm{|g\rangle, |f\rangle}$ encode the logical states and $\mathrm{|e\rangle}$ encodes the erasure state. The integer fluxonium suppresses direct $|\mathrm{f} \rangle \rightarrow |\mathrm{g} \rangle$ transitions and allows the dominant $|\mathrm{f} \rangle \rightarrow |\mathrm{e}\rangle$ transitions to be converted into detectable erasures. Furthermore, we identified a design space that nullifies the resonant-frequency shift between the two logical states, enabling ancilla-free mid-circuit erasure checks using the same resonator employed for final readout. By discarding the detected erasure events, we achieved an 8.4-fold increase in the $|\mathrm{f}\rangle$ state lifetime, a 1.38-fold increase in the Hahn-echo time, and a reduction of single-qubit gate error from 0.061(2)% to 0.030(5)%. Our results establish integer fluxonium as a hardware-efficient platform for erasure-error detection and conversion, while identifying the improvements required to realize an effective erasure qubit with high erasure bias.

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arXiv:2201.03540•Nature Communications•Aug 9, 2022•197 citations
Erasure-error detection can improve the efficiency of quantum error correction by revealing the times and locations of their error events. In this work, we demonstrate erasure conversions and mid-circuit erasure detections in a single integer fluxonium, in which the states ∣g⟩,∣f⟩\mathrm{|g\rangle, |f\rangle}∣g⟩,∣f⟩ encode the logical states and ∣e⟩\mathrm{|e\rangle}∣e⟩ encodes the erasure state. The integer fluxonium suppresses direct ∣f⟩→∣g⟩|\mathrm{f} \rangle \rightarrow |\mathrm{g} \rangle∣f⟩→∣g⟩ transitions and allows the dominant ∣f⟩→∣e⟩|\mathrm{f} \rangle \rightarrow |\mathrm{e}\rangle∣f⟩→∣e⟩ transitions to be converted into detectable erasures. Furthermore, we identified a design space that nullifies the resonant-frequency shift between the two logical states, enabling ancilla-free mid-circuit erasure checks using the same resonator employed for final readout. By discarding the detected erasure events, we achieved an 8.4-fold increase in the ∣f⟩|\mathrm{f}\rangle∣f⟩ state lifetime, a 1.38-fold increase in the Hahn-echo time, and a reduction of single-qubit gate error from 0.061(2)% to 0.030(5)%. Our results establish integer fluxonium as a hardware-efficient platform for erasure-error detection and conversion, while identifying the improvements required to realize an effective erasure qubit with high erasure bias.
Qubits that experience predominantly erasure errors offer distinct advantages for fault-tolerant operation. Indeed, dual-rail encoded erasure qubits in superconducting cavities and transmons have demonstrated high-fidelity operations by converting physical-qubit relaxation into logical-qubit erasures, but this comes at the cost of increased hardware overhead and circuit complexity. Here, we address these limitations by realizing erasure conversion in a single fluxonium operated at zero flux, where the logical state is encoded in its 0-2 subspace. A single, carefully engineered resonator provides both mid-circuit erasure detection and end-of-line (EOL) logical measurement. Post-selection on non-erasure outcomes results in more than four-fold increase of the logical lifetime, from 193 μ193~μ193 μs to 869 μ869~μ869 μs. Finally, we characterize measurement-induced logical dephasing as a function of measurement power and frequency, and infer that each erasure check contributes a negligible error of 7.2×10−57.2\times 10^{-5}7.2×10−5. These results establish integer-fluxonium as a promising, resource-efficient platform for erasure-based error mitigation, without requiring additional hardware.
We propose an erasure conversion scheme on the ∣e⟩−∣f⟩|e\rangle-|f\rangle∣e⟩−∣f⟩ and ∣g⟩−∣f⟩|g\rangle-|f\rangle∣g⟩−∣f⟩ qubits in integer fluxonium qubits (IFQs), which are both first-order insensitive to 1/f1/f1/f flux noise. The ∣e⟩−∣f⟩|e\rangle-|f\rangle∣e⟩−∣f⟩ transition is identical to that of a usual fluxonium qubit and hence is expected to have excellent coherence time, while the ∣g⟩−∣f⟩|g\rangle-|f\rangle∣g⟩−∣f⟩ transition is additionally protected from the energy relaxation by the parity symmetry. The dominant error in both qubits arises due to the energy relaxation: from ∣e⟩|e\rangle∣e⟩ to ∣g⟩|g\rangle∣g⟩ in the e–fe\text{--}fe–f qubit and from ∣f⟩|f\rangle∣f⟩ to ∣e⟩|e\rangle∣e⟩ in the g–fg\text{--}fg–f qubit. Such errors can be treated as erasure events, and their efficient detection improves the performance of quantum error-correcting codes. We consider a protocol for such erasure conversion based on the dispersive readout. Our main finding is that, with proper circuit parameter choice, carefully designed gate sets, and the integration of erasure conversion, IFQs promise high effective coherence times.
Erasure qubits are beneficial for quantum error correction due to their relaxed threshold requirements. While dual-rail erasure qubits have been demonstrated with a strong error hierarchy in circuit quantum electrodynamics, biased-erasure qubits -- where erasures originate predominantly from one logical basis state -- offer further advantages. Here, we realize a hardware-efficient biased-erasure qubit encoded in the vacuum and two-photon Fock states of a single microwave cavity. The qubit exhibits an erasure bias ratio of over 265. By using a transmon ancilla for logical measurements and mid-circuit erasure detections, we achieve logical state assignment errors below 1% and convert over 99.3% leakage errors into detected erasures. After postselection against erasures, we achieve effective logical relaxation and dephasing rates of (6.2 ms)−1(6.2~\mathrm{ms})^{-1}(6.2 ms)−1 and (3.1 ms)−1(3.1~\mathrm{ms})^{-1}(3.1 ms)−1, respectively, which exceed the erasure error rate by factors of 31 and 15, establishing a strong error hierarchy within the logical subspace. These postselected error rates indicate a coherence gain of about 6.0 beyond the break-even point set by the best physical qubit encoded in the two lowest Fock states in the cavity. Moreover, randomized benchmarking with interleaved erasure detections reveals a residual logical gate error of 0.29%. This work establishes a compact and hardware-efficient platform for biased-erasure qubits, promising concatenations into outer-level stabilizer codes toward fault-tolerant quantum computation.
Erasure qubits are a promising platform for implementing hardware-efficient quantum error correction. Realizing the error-correction advantages of this encoding requires frequent mid-circuit erasure checks that are fast, high-fidelity, and scalable. Here, we realize erasure detection with a hardware-efficient circuit consisting of a single readout resonator dispersively and symmetrically coupled to both transmons of a dual-rail qubit. We use this circuit to demonstrate single-shot erasure detection in 384 ns with minimal impact on the dual-rail logical manifold, achieving a residual error per check of 6.0(2)×10−46.0(2) \times 10^{-4}6.0(2)×10−4, with only 8(3)×10−58(3) \times 10^{-5}8(3)×10−5 induced dephasing per check, and an erasure error per check of 2.54(1)×10−22.54(1)\times 10^{-2}2.54(1)×10−2. The high degree of matched dispersive readout coupling (χχχ-matching) within the dual-rail qubit code space also allows us to realize a new modality: time-continuous erasure detection performed in parallel with single-qubit gates. Here we achieve a median 7.2×10−57.2 \times 10^{-5}7.2×10−5 error per gate with <1×10−5< 1 \times 10^{-5}<1×10−5 error induced by erasure detection. This demonstrates a reduction in erasure detection overhead as well as a crucial ingredient for soft information quantum error correction. Together, these results establish symmetrically coupled dispersive readout as a fast, hardware-efficient, and scalable component for erasure-based quantum error correction using transmon dual-rail qubits.
Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states ∣0L⟩\ket{0_\text{L}}∣0L​⟩ and ∣1L⟩\ket{1_\text{L}}∣1L​⟩ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit T1T_1T1​ lifetime exceeding 500 μs500\,μ\mathrm{s}500μs, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the T1T_1T1​ time of the transmon physical qubit. Coherence times beyond 300 μs300\,μ\mathrm{s}300μs are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of 10−410^{-4}10−4. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.
Abstract Executing quantum algorithms on error-corrected logical qubits is a critical step for scalable quantum computing, but the requisite numbers of qubits and physical error rates are demanding for current experimental hardware. Recently, the development of error correcting codes tailored to particular physical noise models has helped relax these requirements. In this work, we propose a qubit encoding and gate protocol for 171 Yb neutral atom qubits that converts the dominant physical errors into erasures, that is, errors in known locations. The key idea is to encode qubits in a metastable electronic level, such that gate errors predominantly result in transitions to disjoint subspaces whose populations can be continuously monitored via fluorescence. We estimate that 98% of errors can be converted into erasures. We quantify the benefit of this approach via circuit-level simulations of the surface code, finding a threshold increase from 0.937% to 4.15%. We also observe a larger code distance near the threshold, leading to a faster decrease in the logical error rate for the same number of physical qubits, which is important for near-term implementations. Erasure conversion should benefit any error correcting code, and may also be applied to design new gates and encodings in other qubit platforms.