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arXiv:2604.16292

Fast, High-Fidelity Erasure Detection of Dual-Rail Qubits with Symmetrically Coupled Readout

Jimmy Shih-Chun Hung, Arbel Haim, Mouktik Raha, Gihwan Kim, Ziwen Huang, Ming-Han Chou, Mitch D'Ewart, Erik Davis, Anurag Mishra, Patricio Arrangoiz Arriola, Amirhossein Khalajhedayati, David Hover, Fernando G. S. L. Brandão, Aashish A. Clerk, Alex Retzker, Harry Levine, Oskar Painter

quant-phSubmitted Apr 17, 2026• Announced Apr 20, 2026• 0 citations
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Abstract

Erasure qubits are a promising platform for implementing hardware-efficient quantum error correction. Realizing the error-correction advantages of this encoding requires frequent mid-circuit erasure checks that are fast, high-fidelity, and scalable. Here, we realize erasure detection with a hardware-efficient circuit consisting of a single readout resonator dispersively and symmetrically coupled to both transmons of a dual-rail qubit. We use this circuit to demonstrate single-shot erasure detection in 384 ns with minimal impact on the dual-rail logical manifold, achieving a residual error per check of $6.0(2) \times 10^{-4}$, with only $8(3) \times 10^{-5}$ induced dephasing per check, and an erasure error per check of $2.54(1)\times 10^{-2}$. The high degree of matched dispersive readout coupling ($χ$-matching) within the dual-rail qubit code space also allows us to realize a new modality: time-continuous erasure detection performed in parallel with single-qubit gates. Here we achieve a median $7.2 \times 10^{-5}$ error per gate with $< 1 \times 10^{-5}$ error induced by erasure detection. This demonstrates a reduction in erasure detection overhead as well as a crucial ingredient for soft information quantum error correction. Together, these results establish symmetrically coupled dispersive readout as a fast, hardware-efficient, and scalable component for erasure-based quantum error correction using transmon dual-rail qubits.

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Quantum error correction with erasure qubits promises significant advantages over standard error correction due to favorable thresholds for erasure errors. To realize this advantage in practice requires a qubit for which nearly all errors are such erasure errors, and the ability to check for erasure errors without dephasing the qubit. We demonstrate that a “dual-rail qubit” consisting of a pair of resonantly coupled transmons can form a highly coherent erasure qubit, where transmon T 1 errors are converted into erasure errors and residual dephasing is strongly suppressed, leading to millisecond-scale coherence within the qubit subspace. We show that single-qubit gates are limited primarily by erasure errors, with erasure probability p erasure = 2.19 ( 2 ) × 10 − 3 per gate while the residual errors are ∼ 40 times lower. We further demonstrate midcircuit detection of erasure errors while introducing < 0.1 % dephasing error per check. Finally, we show that the suppression of transmon noise allows this dual-rail qubit to preserve high coherence over a broad tunable operating range, offering an improved capacity to avoid frequency collisions. This work establishes transmon-based dual-rail qubits as an attractive building block for hardware-efficient quantum error correction. Published by the American Physical Society 2024

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Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states $\ket{0_\text{L}}$ and $\ket{1_\text{L}}$ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit $T_1$ lifetime exceeding $500\,μ\mathrm{s}$, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the $T_1$ time of the transmon physical qubit. Coherence times beyond $300\,μ\mathrm{s}$ are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of $10^{-4}$. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.

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Qubits with predominantly erasure errors present distinctive advantages for quantum error correction (QEC) and fault-tolerant quantum computing. Logical qubits based on dual-rail encoding that exploit erasure detection have been recently proposed in superconducting circuit architectures, with either coupled transmons or cavities. Here, we implement a dual-rail qubit encoded in a compact, double-post superconducting cavity. Using an auxiliary transmon, we perform erasure detection on the dual-rail subspace. We characterize the behavior of the code space by a novel method to perform joint-Wigner tomography. This is based on modifying the cross-Kerr interaction between the cavity modes and the transmon. We measure an erasure rate of 3.981±0.003 (ms)^{-1} and a residual, postselected dephasing error rate up to 0.17 (ms)^{-1} within the code space. This strong hierarchy of error rates, together with the compact and hardware-efficient nature of this novel architecture, holds promise in realizing QEC schemes with enhanced thresholds and improved scaling.

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Hardware-efficient erasure-error detection with an integer fluxonium

Junyoung An, Helin Zhang, Jeffrey M. Gertler +13 more

Erasure-error detection can improve the efficiency of quantum error correction by revealing the times and locations of their error events. In this work, we demonstrate erasure conversions and mid-circuit erasure detections in a single integer fluxonium, in which the states $\mathrm{|g\rangle, |f\rangle}$ encode the logical states and $\mathrm{|e\rangle}$ encodes the erasure state. The integer fluxonium suppresses direct $|\mathrm{f} \rangle \rightarrow |\mathrm{g} \rangle$ transitions and allows the dominant $|\mathrm{f} \rangle \rightarrow |\mathrm{e}\rangle$ transitions to be converted into detectable erasures. Furthermore, we identified a design space that nullifies the resonant-frequency shift between the two logical states, enabling ancilla-free mid-circuit erasure checks using the same resonator employed for final readout. By discarding the detected erasure events, we achieved an 8.4-fold increase in the $|\mathrm{f}\rangle$ state lifetime, a 1.38-fold increase in the Hahn-echo time, and a reduction of single-qubit gate error from 0.061(2)% to 0.030(5)%. Our results establish integer fluxonium as a hardware-efficient platform for erasure-error detection and conversion, while identifying the improvements required to realize an effective erasure qubit with high erasure bias.

quant-pharXiv:2607.27123•Jul 30, 2026•0 citations
Erasure qubits are a promising platform for implementing hardware-efficient quantum error correction. Realizing the error-correction advantages of this encoding requires frequent mid-circuit erasure checks that are fast, high-fidelity, and scalable. Here, we realize erasure detection with a hardware-efficient circuit consisting of a single readout resonator dispersively and symmetrically coupled to both transmons of a dual-rail qubit. We use this circuit to demonstrate single-shot erasure detection in 384 ns with minimal impact on the dual-rail logical manifold, achieving a residual error per check of 6.0(2)×10−46.0(2) \times 10^{-4}6.0(2)×10−4, with only 8(3)×10−58(3) \times 10^{-5}8(3)×10−5 induced dephasing per check, and an erasure error per check of 2.54(1)×10−22.54(1)\times 10^{-2}2.54(1)×10−2. The high degree of matched dispersive readout coupling (χχχ-matching) within the dual-rail qubit code space also allows us to realize a new modality: time-continuous erasure detection performed in parallel with single-qubit gates. Here we achieve a median 7.2×10−57.2 \times 10^{-5}7.2×10−5 error per gate with <1×10−5< 1 \times 10^{-5}<1×10−5 error induced by erasure detection. This demonstrates a reduction in erasure detection overhead as well as a crucial ingredient for soft information quantum error correction. Together, these results establish symmetrically coupled dispersive readout as a fast, hardware-efficient, and scalable component for erasure-based quantum error correction using transmon dual-rail qubits.
Quantum error correction with erasure qubits promises significant advantages over standard error correction due to favorable thresholds for erasure errors. To realize this advantage in practice requires a qubit for which nearly all errors are such erasure errors, and the ability to check for erasure errors without dephasing the qubit. We demonstrate that a “dual-rail qubit” consisting of a pair of resonantly coupled transmons can form a highly coherent erasure qubit, where transmon T 1 errors are converted into erasure errors and residual dephasing is strongly suppressed, leading to millisecond-scale coherence within the qubit subspace. We show that single-qubit gates are limited primarily by erasure errors, with erasure probability p erasure = 2.19 ( 2 ) × 10 − 3 per gate while the residual errors are ∼ 40 times lower. We further demonstrate midcircuit detection of erasure errors while introducing < 0.1 % dephasing error per check. Finally, we show that the suppression of transmon noise allows this dual-rail qubit to preserve high coherence over a broad tunable operating range, offering an improved capacity to avoid frequency collisions. This work establishes transmon-based dual-rail qubits as an attractive building block for hardware-efficient quantum error correction. Published by the American Physical Society 2024
Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states ∣0L⟩\ket{0_\text{L}}∣0L​⟩ and ∣1L⟩\ket{1_\text{L}}∣1L​⟩ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit T1T_1T1​ lifetime exceeding 500 μs500\,μ\mathrm{s}500μs, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the T1T_1T1​ time of the transmon physical qubit. Coherence times beyond 300 μs300\,μ\mathrm{s}300μs are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of 10−410^{-4}10−4. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.
Qubits that experience predominantly erasure errors offer distinct advantages for fault-tolerant operation. Indeed, dual-rail encoded erasure qubits in superconducting cavities and transmons have demonstrated high-fidelity operations by converting physical-qubit relaxation into logical-qubit erasures, but this comes at the cost of increased hardware overhead and circuit complexity. Here, we address these limitations by realizing erasure conversion in a single fluxonium operated at zero flux, where the logical state is encoded in its 0-2 subspace. A single, carefully engineered resonator provides both mid-circuit erasure detection and end-of-line (EOL) logical measurement. Post-selection on non-erasure outcomes results in more than four-fold increase of the logical lifetime, from 193 μ193~μ193 μs to 869 μ869~μ869 μs. Finally, we characterize measurement-induced logical dephasing as a function of measurement power and frequency, and infer that each erasure check contributes a negligible error of 7.2×10−57.2\times 10^{-5}7.2×10−5. These results establish integer-fluxonium as a promising, resource-efficient platform for erasure-based error mitigation, without requiring additional hardware.
Qubits with predominantly erasure errors present distinctive advantages for quantum error correction (QEC) and fault-tolerant quantum computing. Logical qubits based on dual-rail encoding that exploit erasure detection have been recently proposed in superconducting circuit architectures, with either coupled transmons or cavities. Here, we implement a dual-rail qubit encoded in a compact, double-post superconducting cavity. Using an auxiliary transmon, we perform erasure detection on the dual-rail subspace. We characterize the behavior of the code space by a novel method to perform joint-Wigner tomography. This is based on modifying the cross-Kerr interaction between the cavity modes and the transmon. We measure an erasure rate of 3.981±0.003 (ms)^{-1} and a residual, postselected dephasing error rate up to 0.17 (ms)^{-1} within the code space. This strong hierarchy of error rates, together with the compact and hardware-efficient nature of this novel architecture, holds promise in realizing QEC schemes with enhanced thresholds and improved scaling.
Erasure qubits are beneficial for quantum error correction due to their relaxed threshold requirements. While dual-rail erasure qubits have been demonstrated with a strong error hierarchy in circuit quantum electrodynamics, biased-erasure qubits -- where erasures originate predominantly from one logical basis state -- offer further advantages. Here, we realize a hardware-efficient biased-erasure qubit encoded in the vacuum and two-photon Fock states of a single microwave cavity. The qubit exhibits an erasure bias ratio of over 265. By using a transmon ancilla for logical measurements and mid-circuit erasure detections, we achieve logical state assignment errors below 1% and convert over 99.3% leakage errors into detected erasures. After postselection against erasures, we achieve effective logical relaxation and dephasing rates of (6.2 ms)−1(6.2~\mathrm{ms})^{-1}(6.2 ms)−1 and (3.1 ms)−1(3.1~\mathrm{ms})^{-1}(3.1 ms)−1, respectively, which exceed the erasure error rate by factors of 31 and 15, establishing a strong error hierarchy within the logical subspace. These postselected error rates indicate a coherence gain of about 6.0 beyond the break-even point set by the best physical qubit encoded in the two lowest Fock states in the cavity. Moreover, randomized benchmarking with interleaved erasure detections reveals a residual logical gate error of 0.29%. This work establishes a compact and hardware-efficient platform for biased-erasure qubits, promising concatenations into outer-level stabilizer codes toward fault-tolerant quantum computation.
Erasure-error detection can improve the efficiency of quantum error correction by revealing the times and locations of their error events. In this work, we demonstrate erasure conversions and mid-circuit erasure detections in a single integer fluxonium, in which the states ∣g⟩,∣f⟩\mathrm{|g\rangle, |f\rangle}∣g⟩,∣f⟩ encode the logical states and ∣e⟩\mathrm{|e\rangle}∣e⟩ encodes the erasure state. The integer fluxonium suppresses direct ∣f⟩→∣g⟩|\mathrm{f} \rangle \rightarrow |\mathrm{g} \rangle∣f⟩→∣g⟩ transitions and allows the dominant ∣f⟩→∣e⟩|\mathrm{f} \rangle \rightarrow |\mathrm{e}\rangle∣f⟩→∣e⟩ transitions to be converted into detectable erasures. Furthermore, we identified a design space that nullifies the resonant-frequency shift between the two logical states, enabling ancilla-free mid-circuit erasure checks using the same resonator employed for final readout. By discarding the detected erasure events, we achieved an 8.4-fold increase in the ∣f⟩|\mathrm{f}\rangle∣f⟩ state lifetime, a 1.38-fold increase in the Hahn-echo time, and a reduction of single-qubit gate error from 0.061(2)% to 0.030(5)%. Our results establish integer fluxonium as a hardware-efficient platform for erasure-error detection and conversion, while identifying the improvements required to realize an effective erasure qubit with high erasure bias.