We present the design and benchmarking of RP000, a quantum photonic processor capable of encoding a quantum system in the degrees of freedom of single photons, based on standard CMOS-compatible manufacturing processes, and working at room temperature. We benchmark it against machine learning tasks, evaluating three quantum-classical architectures of increasing complexity. Our experimental results and simulations show that RP000 achieves higher accuracy than classical networks of comparable size in multiple use cases. Compared to a superconducting quantum processor, RP000 exhibits superior noise tolerance. These findings demonstrate that RP000 can provide a scalable route toward efficient quantum applications.
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Accepted at the 2026 IEEE International Conference on Quantum Computing and Engineering (QCE)
We present the design and benchmarking of RP000, a quantum photonic processor capable of encoding a quantum system in the degrees of freedom of single photons, based on standard CMOS-compatible manufacturing processes, and working at room temperature. We benchmark it against machine learning tasks, evaluating three quantum-classical architectures of increasing complexity. Our experimental results and simulations show that RP000 achieves higher accuracy than classical networks of comparable size in multiple use cases. Compared to a superconducting quantum processor, RP000 exhibits superior noise tolerance. These findings demonstrate that RP000 can provide a scalable route toward efficient quantum applications.
Artificial intelligence and machine learning have been widely adopted both in the industry and in everyday life, but at the cost of high compute demands. Recent studies show that implementing machine learning in physical systems in the deep quantum regime could not only lead to faster information processing, but also to perform tasks that are out of reach for classical systems. Here, we report a quantum reservoir processing device capable of performing both quantum and classical machine learning tasks. The implementation is realized with a programmable silicon chip excited with single photons, a highly scalable and adaptable photonics technology. We successfully implement a variety of quantum tasks, including quantum state tomography and measurement of entanglement via negativity. Moreover, we implement a method of mitigation of experimental imperfections which results in a significant improvement in accuracy in comparison to the same system operating in the classical regime. Our results demonstrate a method to overcome a crucial bottleneck of quantum technologies by providing a practical way of probing quantum states.
In recent years, quantum information has rapidly evolved as a field with transformative potential in science and technology. It provides secure encryption for communication, accurate emulation of practical physical systems, streamlined and accelerated machine learning models, and advanced computational powers that outperform classical supercomputers in solving complex problems. These advancements are all reliant on the superposition and entanglement properties of qubits. While various candidates such as trapped ions or superconducting qubits have been proposed to realize quantum technologies, photons have demonstrated a prominent advantage due to their robustness against decoherence and noise, high clock cycle rate, fast and easy measurement, and room temperature working environment. In addition, photonic integrated chip (PIC) technology has developed rapidly since the beginning of the 21st century. The number of devices integrated on a single chip has increased rapidly, and its complexity has also increased. Quantum computing combined with integrated photonics is expected to solve bottleneck problems in practical situations. In this thesis, based on the silicon-on-insulator (SOI) platform, an optical computing chip and a large-scale quantum computing chip with various practical applications are specifically studied. In the first part of the thesis, a novel integrated diffractive optical network is studied, and a scheme is designed to realize parallel Fourier transform, convolution operations, and application-specific optical computing. Due to the utilization of on-chip compact diffractive cells (slab waveguides), the footprint and power consumption of the proposed architecture is reduced from quadratic scaling in the input data dimensions required for Mach-Zehnder interferometer (MZI)-based optical neural network (ONN) architectures to linear scaling for the improved deep neural networks. A 10-fold reduction in both footprint and energy consumption and equal high accuracy with previous MZI-based ONNs was experimentally achieved for computations performed on the Modified National Institute of Standards and Technology (MNIST) and Fashion-MNIST datasets. This reduction in the resource scaling from quadratic to linear has a profound impact on the realization of large-scale silicon-photonics computing circuits with current fabrication technologies. A quantum photonic microprocessor based on Gaussian Boson sampling (GBS) that offers dynamic programmability to solve various graph-related NP-complete problems is then demonstrated. The system with optical, electrical, and thermal packaging implements a GBS with 16 modes of single-mode squeezed vacuum states, a universal programmable 16-mode interferometer, and a single photon readout on all outputs with high accuracy, generality, and controllability. The developed system is applied to demonstrate applications in solving NP-complete problems, manifesting the ability of photonic quantum computing to realize practical applications for conventionally intractable computations. The GBS-based quantum photonic microprocessor is applied to solve task assignment, Boolean satisfiability, graph clique, max cut, and vertex cover. These demonstrations suggest an excellent benchmarking platform, paving the way toward large-scale combinatorial optimization. Finally, this thesis explores the application possibility of large-scale PICs in molecular simulation. A new algorithm utilizing states with zero displacements (vacuum-squeezed states) coupling to a linear network is proposed to calculate molecular vibronic spectra. With a large-scale PIC, molecular vibronic spectra are accurately simulated for formic acid and thymine with high reconstructed fidelity (>91%) and for naphthalene, phenanthrene, and benzene under the non-Condon regime. Our experimental demonstration will open pathways toward conducting large-scale molecular quantum simulations, a task surpassing classical computers’ capabilities.
We propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of$\sim$2–20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78–84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.
Scaling fault-tolerant superconducting quantum computers will likely require distributed architectures built from multiple manufacturable quantum processing units. A central question is whether noisy and slow inter-chip operations impose substantial spacetime overhead or orchestration burdens compared with monolithic architectures. To answer this question, we present a hardware-grounded architectural co-design together with a comprehensive resource-estimation protocol for surface-code-based modular processors. The design confines inter-chip latency and noise to module boundaries, preventing slow, noisy links from inducing prohibitive spacetime overhead or becoming a global orchestration bottleneck. The resource-estimation protocol integrates hardware constraints and circuit-level error-correction performance into utility-scale algorithmic cost estimates, enabling a controlled assessment of different architectures. Using RSA-2048 factorization as a demanding benchmark, we estimate resources under experimentally anchored parameters and realistic superconducting hardware constraints. Compared with a large, ideal monolithic baseline, the resulting distributed architecture requires only modest additional resource overhead in both qubit count and execution time. More importantly, the overhead is nearly scale-invariant across a broad module-capacity window, decoupling chip size from global performance. This decoupling turns module capacity from a finely tuned architectural parameter into a flexible engineering degree of freedom, allowing chip sizes to be set by manufacturability and control-packaging constraints rather than architectural fine-tuning. These results establish a viable route to distributed fault-tolerant superconducting quantum computation that scales without prohibitive resource growth or heavy orchestration burden.
Abstract We present a quantum-analogous experimental demonstration of variational quantum process tomography using an optical processor. This approach leverages classical one-hot encoding and unitary decomposition to perform the variational quantum algorithm on a photonic platform. We create the first benchmark for variational quantum process tomography evaluating the performance of the quantum-analogous experiment on the optical processor against several publicly accessible quantum computing platforms, including IBM’s 127-qubit Sherbrooke processor, QuTech’s five-qubit Tuna-5 processor, and Quandela’s 12-mode Ascella quantum optical processor. We evaluate each method using process fidelity, cost function convergence, and processing time per iteration for variational quantum circuit depths of d = 3 and d = 6. Our results indicate that the optical processors outperform their superconducting counterparts in terms of fidelity and convergence behavior reaching fidelities of 0.8 after nine iterations, particularly at higher depths, where the noise of decoherence and dephasing affect the superconducting processors significantly. We further investigate the influence of any additional quantum optical effects in our platform relative to the classical one-hot encoding. From the process fidelity results it shows that the (classical) thermal noise in the phase-shifters dominates over other optical imperfections, such as mode mismatch and dark counts from single-photon sources. The benchmarking framework and experimental results demonstrate that photonic processors are strong contenders for near-term quantum algorithm deployment, particularly in hybrid variational contexts. This analysis is valuable not only for state and process tomography but also for a wide range of applications involving variational quantum circuit based algorithms.