Multi-core quantum computing architectures have emerged as a promising solution to the qubit scalability limitations of monolithic NISQ devices. Quantum algorithms are expressed as quantum circuits composed of single- and two-qubit gates. However, circuit scheduling in multi-core quantum systems remains largely unexplored. Reducing overall execution time (makespan), increasing core utilization, and hiding communication latency behind computation depends on effective scheduling. In this paper, we first introduce a layered scheduling approach as a baseline where quantum gates within the same layer are executed in parallel, while layers themselves are executed sequentially. We then propose a greedy scheduling strategy which schedules each gate as soon as all its dependencies and required resources are available. This allows fine-grained parallelism across cores. Our evaluation shows that on real benchmarks, greedy scheduling achieves an average 40% reduction in makespan and improvement in core utilization. The results suggest that the use of intelligent circuit scheduling to exploit parallelism can greatly enhance the speed of circuit execution in multi-core quantum architectures.
Multi-core quantum computing architectures have emerged as a promising solution to the qubit scalability limitations of monolithic NISQ devices. Quantum algorithms are expressed as quantum circuits composed of single- and two-qubit gates. However, circuit scheduling in multi-core quantum systems remains largely unexplored. Reducing overall execution time (makespan), increasing core utilization, and hiding communication latency behind computation depends on effective scheduling. In this paper, we first introduce a layered scheduling approach as a baseline where quantum gates within the same layer are executed in parallel, while layers themselves are executed sequentially. We then propose a greedy scheduling strategy which schedules each gate as soon as all its dependencies and required resources are available. This allows fine-grained parallelism across cores. Our evaluation shows that on real benchmarks, greedy scheduling achieves an average 40% reduction in makespan and improvement in core utilization. The results suggest that the use of intelligent circuit scheduling to exploit parallelism can greatly enhance the speed of circuit execution in multi-core quantum architectures.
Distributed multi-QPU infrastructures share scarce devices across many users, making circuit scheduling a key systems-software challenge. Major providers (Amazon, Microsoft, IBM, Quantinuum) still rely on simple priority-based FIFO strategies that preserve fairness but ignore coordinated multi-QPU execution. We propose priority-aware scheduling that casts quantum circuit scheduling as a classical packing problem, integrates with distributed quantum software stacks, and is released as an open-source implementation. Experiments show a 47% reduction in makespan and a 77% throughput increase over industry FIFO, and a 23% improvement over the strongest academic baseline.
Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate.
Distributed quantum computing (DQC) has emerged as a promising approach to overcome the scalability limitations of monolithic quantum processors in terms of computational capability. However, realising the full potential of DQC requires effective resource management and circuit scheduling. This involves efficiently assigning each circuit to a subset of quantum processing units (QPUs), based on factors such as their computational power and connectivity. In heterogeneous DQC networks with arbitrary connectivity topologies and non-identical QPUs, this becomes a complex challenge. This paper addresses resource management and circuit scheduling in such settings, with a focus on computing resource allocation in a quantum data centre. We propose circuit scheduling algorithms based on Mixed-Integer Linear Programming (MILP). Our MILP model accounts for errors arising from inter-QPU communication. In particular, the proposed schemes consider key factors, including network topology, QPU capacities, and quantum circuit structure, to make efficient scheduling and allocation decisions. Simulation results demonstrate that our proposed algorithms significantly improve circuit execution time and scheduling efficiency (measured by makespan and throughput), while also reducing inter-QPU communication overhead, compared to baseline strategies. This work provides valuable insights into resource management strategies for scalable and heterogeneous DQC systems.
Current quantum computing platforms often exhibit suboptimal hardware utilization, with most circuits engaging only a fraction of the available qubits. This inefficiency inflates execution costs, extends queueing times, and hampers scalability, particularly in shared, cloud-based environments. This paper introduces a service-oriented architecture for the parallel execution of quantum circuits that jointly schedules and executes logically independent circuits within a single task. The service supports multiple configurable scheduling policies, based on criteria such as circuit depth, number of qubits, and number of shots, and ensures logical separation of circuits with accurate result demultiplexing. Extensive validation on real quantum hardware, including IBM and AWS processors, demonstrates significant improvements: task submission reductions of up to 95%, cost savings of up to 93%, and fidelity levels exceeding 97% even under high utilization. This solution offers a reusable, extensible approach that enhances resource efficiency and performance in Quantum Computing as a Service platforms.
The current execution model of quantum computers, based on serialized task processing, leads to inefficient resource utilization and increased waiting times. This inefficiency persists even as the demand for quantum computing grows. To address this, an automated scheduling approach is proposed through the AutoScheduler library, which replicates quantum circuits to fully occupy the available qubits in a quantum processor. This strategy reduces the number of required shots per execution while optimizing hardware usage. Experimental validation on IBM Quantum and Amazon Braket platforms demonstrates that autoscheduling achieves substantial reductions in execution time and cost, with minimal impact on result fidelity despite inherent quantum noise. These findings suggest that circuit autoscheduling is a viable method for improving the scalability and efficiency of quantum computing in the NISQ era.
Proposing an architecture that effectively compensates for physical hardware inefficiencies through redundant resources is a key challenge in quantum computer design. Although the representation of quantum systems is currently limited to tens of qubits, scaling existing small scale laboratory systems into large scale quantum computers capable of solving meaningful practical problems remains a primary research objective. Focusing on this issue, this paper proposes a scalable architecture for quantum information processors. Physical design, one of the two main processes in quantum computer design, transforms a circuit netlist into a technology specific layout. Quantum mapping comprising partitioning, placement, scheduling, and routing is an essential part of this process, and these stages are inherently interdependent. In this research, considering the dependencies between these stages, we present an Integer Linear Programming (ILP) model for qubit partitioning and placement, determining the optimal module and physical location for each qubit. Furthermore, we propose a heuristic approach for the placement and scheduling of quantum operators on a scalable, modular, universal ion trap quantum computer (MUSIQC), aiming to minimize circuit execution delay. Qubit routing is performed using a greedy strategy. For evaluation, the proposed method was applied to both Ripple-Carry Adder and Carry-Lookahead Adder circuits. Experimental results demonstrate that the proposed approach reduces the average circuit delay by approximately 58.98% for Ripple-Carry Adder circuits and 33% for Carry-Lookahead Adder circuits compared to the best existing method. These results underscore the effectiveness of our integrated framework, where ILP-based partitioning optimizes for dominant operational costs, while our subsequent resource-aware scheduler actively manages parallelism and contention to achieve the minimal overall circuit execution delay.