Quantum computing is progressing beyond experimental prototypes toward cloud-based services and commercially deployed turnkey systems. Evaluating and comparing platform performance requires robust, standardized measures, yet vendors frequently report heterogeneous metrics that are not directly comparable or may not capture whole-system performance. Peaked Random Circuits (PRCs) have recently been proposed as a viable path to demonstrate quantum advantage: a quantum processor can reliably identify a single known high-probability outcome while the circuits' inherent complexity may render classical simulation infeasible. To support robust, system-level evaluation and comparison, we propose a novel benchmarking protocol based on PRCs. By successively running a set of PRCs with varying qubit counts and circuit depths, we quantify a system's ability to identify the deterministic peak despite cumulative noise, gate errors, and connectivity constraints. We demonstrate the benchmark experimentally on IQM's superconducting and AQT's trapped-ion architectures. Our results show that the PRC benchmark provides a holistic yet high-precision view of hardware performance and offers researchers and industry stakeholders a practical and scalable framework for the continuous comparison and evaluation of current and future quantum systems.
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V2: Updated and expanded. Added details on the sampling strategy in Section 3, restructured Sections 5 and 6, and illustrated the benchmarking protocol in Section 5
Quantum computing is progressing beyond experimental prototypes toward cloud-based services and commercially deployed turnkey systems. Evaluating and comparing platform performance requires robust, standardized measures, yet vendors frequently report heterogeneous metrics that are not directly comparable or may not capture whole-system performance. Peaked Random Circuits (PRCs) have recently been proposed as a viable path to demonstrate quantum advantage: a quantum processor can reliably identify a single known high-probability outcome while the circuits' inherent complexity may render classical simulation infeasible. To support robust, system-level evaluation and comparison, we propose a novel benchmarking protocol based on PRCs. By successively running a set of PRCs with varying qubit counts and circuit depths, we quantify a system's ability to identify the deterministic peak despite cumulative noise, gate errors, and connectivity constraints. We demonstrate the benchmark experimentally on IQM's superconducting and AQT's trapped-ion architectures. Our results show that the PRC benchmark provides a holistic yet high-precision view of hardware performance and offers researchers and industry stakeholders a practical and scalable framework for the continuous comparison and evaluation of current and future quantum systems.
Quantum computers have now surpassed classical simulation limits, yet noise continues to limit their practical utility. As the field shifts from proof-of-principle demonstrations to early deployments, there is no standard method for meaningfully and scalably comparing heterogeneous quantum hardware. Existing benchmarks typically focus on gate-level fidelity or constant-depth circuits, offering limited insight into algorithmic performance at depth. Here we introduce a benchmarking protocol based on the linear ramp quantum approximate optimization algorithm (LR-QAOA), a fixed-parameter, deterministic variant of QAOA. LR-QAOA quantifies a QPU's ability to preserve a coherent signal as circuit depth increases, identifying when performance becomes statistically indistinguishable from random sampling. We apply this protocol to 24 quantum processors from six vendors, testing problems with up to 156 qubits and 10,000 layers across 1D-chains, native layouts, and fully connected topologies. This constitutes the most extensive cross-platform quantum benchmarking effort to date, with circuits reaching a million two-qubit gates. LR-QAOA offers a scalable, unified benchmark across platforms and architectures, making it a tool for tracking performance in quantum computing.
While fundamental scientific researchers are eagerly anticipating the breakthroughs of quantum computing both in theory and technology, the current quantum computer, i.e. noisy intermediate-scale quantum (NISQ) computer encounters a bottleneck in how to deal with the noisy situation of the quantum machine. It is still urgently required to construct more efficient and reliable benchmarking protocols through which one can assess the noise level of a quantum circuit that is designed for a quantum computing task. The existing methods that are mainly constructed based on a sequence of random circuits, such as randomized benchmarking (RB), have been commonly adopted as the conventional approach owning to its reasonable resource consumption and relatively acceptable reliability, compared with the average gate fidelity. To more deeply understand the performances of the above different randomized-framed benchmarking protocols, we design special random circuit sequences to test the performances of the three selected standard randomized-frame protocols under T1, T2, and coherent errors, which are regarded to be more practical for a superconductor quantum computer. The simulations indicate that MRB, DRB, and CRB sequentially overestimate the average error rate in the presence of T1 and T2 noise, compared with the conventional circuit's average error. Moreover, these methods exhibit almost the same level of sensitivity to the coherent error. Furthermore, the DRB loses its reliability when the strengths of T1 grow. More practically, the simulated conclusion is verified by running the designed tasks for three protocols on the Quafu quantum computation cloud platform. We find that MRB produces a more precise assessment of a quantum circuit conditioned on limited resources. However, the DRB provides a more stable estimation at a specific precision while a more resource-consuming.
With the advent of more quantum computing applications, it is imperative to provide developers with a set of metrics to determine how much trust they can place in the execution of their programs. In this study, we propose a novel protocol based on quantum teleportation to systematically evaluate the performance of quantum circuits and quantify their execution reliability. Our protocol consists of three parts: the payload, composed of entangled qubits with random gates applied to each wire; the bridge, which corresponds to the teleportation-inspired protocol; and an inverse payload operation, designed to return the circuit to its initial state. We validated the algorithm by elaborating its mathematical framework, followed by a comparative analysis with simulation results using Qiskit AerSimulator and ultimately through an execution on the IBM quantum and Rigetti services. A key aspect of our methodology was to set the circuit transpilation to its lowest optimization level (level 0). We recognize that even without aggressive optimization, randomly generated gates can form self-canceling sequences. As a result, our analysis correlates the pre-runtime metrics of the final, minimally-transpiled circuit (such as its actual depth and gate count) with post-runtime results (such as success rate). This approach reveals significant correlations and offers developers quantitative metrics to assess both the reliability of quantum circuit execution and scalability limitations in their applications.
This research paper provides an in-depth examination of verification and testing approaches for quantum circuits, focusing on methodologies essential for ensuring the correctness, reliability and operational efficiency of quantum computing systems. Since quantum circuits function on the fundamental principles of superposition and entanglement, they present verification challenges that cannot be effectively addressed using conventional classical testing techniques. As a result, the development of specialized quantum-specific verification strategies has become critically important. The study highlights simulation-based verification as a foundational technique, wherein the outcomes of quantum circuit simulations are systematically compared with results obtained from physical quantum hardware. This process enables the identification of functional inconsistencies and supports iterative refinement of circuit designs. In addition, randomized benchmarking is examined as a key evaluation method for estimating circuit fidelity and quantifying error rates through the application of random gate sequences and performance comparisons against established benchmarks. To further improve system robustness, the research investigates fault-tolerant mechanisms, particularly quantum error correction codes, which play a vital role in minimizing the effects of noise, decoherence and hardware imperfections. The integration of advanced quantum metrology and characterization techniques is also explored, enabling precise measurement and detailed analysis of quantum system behavior. These techniques provide deeper insights into circuit performance and contribute significantly to validation processes. By combining simulation-based verification, randomized benchmarking, fault-tolerant protocols and quantum metrology, this study proposes a comprehensive and reliable framework for quantum circuit verification and testing. The findings contribute to the advancement of dependable quantum technologies and support their growing applications in areas such as cryptography, materials science and other emerging domains.
Recent advances in quantum computing have enabled the development of quantum processors with hundreds of qubits. However, noise continues to limit the amount of useful information that can be extracted from these systems, making it essential to identify the regime in which experimental outputs remain reliable. In this work, we benchmark Quantinuum Helios-1, a 98-qubit trapped-ion quantum processing unit, using the linear ramp quantum approximate optimization algorithm (LR-QAOA). To this end, we perform large-scale noiseless simulations on JUPITER, Europe's first exascale supercomputer, for circuits of up to 48 qubits and 3,384 two-qubit gates. These simulations, executed on 4,096 nodes equipped with 16,384 GH200 superchips and high-bandwidth CPU-GPU interconnects, provide a reference for validating experimental results at the edge of classical tractability. We find that, up to 48 qubits, Helios-1 remains in a noise-tolerant region, i.e., its samples cannot be clearly distinguished from those coming from a noiseless simulation. We then extend the analysis to larger system sizes using experimental data only, and apply a mean-of-means resampling procedure with a 3σ threshold to determine whether the QPU output is statistically distinguishable from random sampling. This analysis identifies a regime of coherent performance up to 93 qubits (12,834 two-qubit gates), beyond which, at 95 qubits, the outputs become statistically indistinguishable from random sampling. These results demonstrate how exascale classical simulation can be used to validate quantum processors, and provide a quantitative boundary between noise-tolerant and random regimes in quantum processors.
The development of complex circuits for practical applications in the current quantum computing ecosystem is based on basic primitives such as Bell states, which provide superposition, entanglement, and coherence. The range of domain-specific quantum applications has been greatly expanded by the availability of simulators and platforms such as IBM Quantum, which are supported by Qiskit. However, disparities between ideal simulator outputs and actual quantum processing unit (QPU) executions in the Noisy Intermediate-Scale Quantum (NISQ) era require the application of quantum error mitigation techniques. Limitations arise from hardware constraints in superconducting qubit systems and from the limited resources of classical simulators as quantum circuits grow. Quantum decoherence, which lowers gate fidelity and builds up at the circuit level with increasing depth, is specifically caused by material-induced flaws and interfaces. This creates a clear connection between circuit reliability, device performance, and material attributes. To address this, the current work uses both simulation and actual hardware on the IBM Sherbrooke 127-qubit processor to study three basic circuit classes over 4 to 10 qubits: the quantum Fourier transform, the Greenberger-Horne-Zeilinger state, and the W state. The study examines trade-offs between circuit complexity, noise robustness, and resource utilization by contrasting simulator and QPU results. The results imply that circuit fidelity can serve as an indirect probe of material-limited noise, opening the door to a framework for designing quantum circuits that accounts for both hardware and materials to achieve scalable quantum advantage.