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arXiv:2605.10708 · Quantum Science and Technology

Gate-Level Quantum Simulation of Nonunitary Linear Dynamics with Hybrid Oscillator-Qubit Architecture

Elin Ranjan Das, Muqing Zheng, Rishab Dutta, Ang Li, Timothy Stavenger, Yuan Liu

quant-phSubmitted May 11, 2026• Announced May 12, 2026• 0 citations• Revised Jul 27, 2026 (v2)
v1 · May 11, 2026v2 · Jul 27, 2026v3 · Aug 21, 2026
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Abstract

We realize the one-mode unitary dilation of nonunitary linear dynamics as a gate-level hybrid oscillator--qubit architecture. An oscillator encodes the kernel by state preparation and postselection, while a qubit register simulates the discretized operator for $\dot u=-(L+iH)u$, including discretized PDEs. One oscillator replaces the $O(\log M_a)$ ancilla qubits in a DV $M_a$-term quadrature register. The ideal kernel state's squeezed-Fock projection error decays superalgebraically with cutoff $N$ for Schwartz-class kernels and stretched-exponentially under stronger joint decay and smoothness conditions. Its generic stellar rank $N-1$ makes $N$ a measure of the state's non-Gaussian resource. A $p$th-order product formula requires $O(t^{1+1/p}N_{\mathrm{Fock}}^{(p+1)/(2p)}ε_t^{-1/p})$ worst-case Trotter steps for oscillator dimension $N_{\mathrm{Fock}}$, up to generator-dependent commutator factors. A perturbation bound separates scaled-map error from physical postselection probability. We benchmark Law--Eberly synthesis and assess variational SNAP+D state preparation for heat equations. Full circuit maps of one-dimensional heat and non-normal advection--diffusion instances up to $D=32$ have at most $1.48\%$ fixed-scale error and $4.68\times10^{-4}$ conditional infidelity over all computational-basis inputs. At the same kernel parameters, a $4\times4$ two-dimensional stress case reaches $7.40\%$ fixed-scale error as stronger damping reduces the reference norm, with worst-input conditional infidelity $6.20\times10^{-3}$. At the prescribed DV sizing, the hybrid route has smaller fixed-scale error in all ten instances, while the DV route accepts with fewer repetitions in every instance. This block-by-block finite-size resource account identifies when one qumode can replace a discretized ancilla register.

DOI
10.1088/2058-9565/aea2c6

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Hybrid continuous-variable--discrete-variable (CV--DV) architectures process quantum information in bosonic modes and qubits, but noise limits their performance. To reduce the noise, existing DV error correction must be complemented by CV noise reduction. Existing CV noise-reduction schemes -- such as GKP-stabilizer codes -- can reduce CV noise, but only for Gaussian gates. Therefore, no current noise-reduction scheme can correct arbitrary CV--DV gates, including non-Gaussian ones. Here, we develop noise reduction for a universal CV--DV gate set, making it applicable to arbitrary CV--DV gates. We do so by introducing an ancilla qubit into a GKP-stabilizer code, allowing us to reduce the standard deviation of Gaussian displacement noise from σσσ to O~(σ2)\tilde O(σ^2)O~(σ2). To demonstrate the scheme, we show that it significantly reduces noise and improves fidelity in the preparation of non-Gaussian cat and Fock states.
Hybrid continuous-variable (CV)-discrete-variable (DV) quantum systems present a promising direction for quantum computing by combining the high dimensional encoding capabilities of qumodes with the control offered by DV qubits on the coupled qumodes. There have been exciting recent progresses on hybrid CV-DV quantum computing, including variational algorithms, error correction, compiler-level optimizations for Hamiltonian simulation, etc. However, there is a lack of a standardized CV-DV benchmark suite for assessing various emerging hardware platforms and evaluating software optimizations on hybrid CV-DV circuits. In this work, we introduce a simulation and benchmarking framework for hybrid CV-DV circuits, implemented using Bosonic Qiskit-a tool specifically designed to model CV-DV systems, along with QuTip for functional correctness verification. We construct and characterize representative CV-DV benchmarks, including cat state generation, GKP state generation, CV-DV state transfers, hybrid quantum Fourier transform, variational quantum algorithms, Hamiltonian simulation, and Shor's algorithm. To assess circuit complexity and scalability, we define a feature map organized into two categories: general features (e.g., qubit/qumode count, gate counts) and CV-DV-specific features (e.g., Wigner negativity, energy, truncation cost). These metrics enable evaluation of both classical simulability and hardware resource requirements. Our results, including one benchmark on real hardware, demonstrate that hybrid CV-DV architectures are not only viable but well-suited for a range of computational tasks, from optimization to Hamiltonian simulation. This framework lays the groundwork for systematic evaluation and future development of hybrid quantum systems.
This tutorial offers a pedagogical guide to hybrid quantum processors that integrate discrete-variable (DV) qubits and continuous-variable (CV) oscillators. Aimed at computer scientists, engineers, and physicists, it provides an overview of the experimental, algorithmic, and architectural aspects of this novel and rapidly developing hardware model. Experimental realizations of this model include superconducting, trapped-ion, and neutral-atom platforms. By combining DV and CV components, hybrid oscillator-qubit processors enable a powerful new paradigm that offers complementary strengths for quantum control, error correction, computation, and simulation. Working toward the goal of a full-stack system connecting applications to CV-DV hardware, we define and formulate abstract machine models and instruction set architectures. These essential abstractions enable codesign of hardware and software, and resource estimation for exploring the potential of current and future hardware for computational and simulation tasks. Using these abstractions, we present both new and existing examples that illustrate the benefits of hybrid CV-DV processors relative to traditional DV-only hardware in computation as well as quantum simulation of physical models. Examples include algorithms for transferring states between DV and CV systems, performing the quantum Fourier transform, and simulation of lattice gauge theories. Relative to qubit-only hardware, the bosonic degrees of freedom natively available in hybrid architectures can substantially reduce the circuit complexity of simulations for physical models containing bosons. A key technique is the extension of quantum signal processing ideas to CV-DV systems. This work is intended to serve as a timely and comprehensive guide to this relatively unexplored yet promising approach to quantum computation and to provide a road map to guide future development.
The realization of universal control in hybrid oscillator-qubit quantum processors enables the systematic design and implementation of quantum algorithms. However, the algorithmic development for such platforms remains at an early stage. While the Quantum Approximate Optimization Algorithm (QAOA) has been extensively studied in both continuous-variable (CV) and discrete-variable (DV) quantum systems, its development in the hybrid CV-DV setting remains limited. In this paper, we propose a hardware-native non-Abelian mixer for QAOA on hybrid CV-DV quantum processors and develop a corresponding hybrid ansatz for the Max-Cut problem. We evaluate the proposed ansatz on unweighted Erdős-Rényi graphs and benchmark it against the standard transverse-field mixer using the approximation ratio and optimal-solution probability. Across all graph sizes and Fock cutoffs in our simulations, the proposed non-Abelian mixer consistently improves both expected solution quality and the probability of sampling an optimal solution relative to the transverse-field mixer. These results indicate that the proposed non-Abelian mixer is a promising building block for QAOA on hybrid oscillator-qubit platforms.