Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2603.21537

High-yield integration design of fixed-frequency superconducting qubit systems using siZZle-CZ gates

Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro

quant-phSubmitted Mar 23, 2026• Announced Mar 24, 2026• 0 citations• Revised Mar 24, 2026 (v2)
v1 · Mar 23, 2026v2 · Mar 24, 2026
arXivHTMLPDF

Abstract

Fixed-frequency transmon qubits, characterized by simple architectures and long coherence times, are promising platforms for large-scale quantum computing. However, the rapidly increasing frequency collisions, which directly reduce the fabrication yield, hinder scaling, especially in cross-resonance (CR) gate-based architectures, wherein the restricted drive frequency severely limits the available design space. We investigate the Stark-induced ZZ by level excursions (siZZle) gate, which relaxes this limitation by allowing arbitrary drive-frequency choices. Extensive numerical analyses across a broad parameter range -- including the far-detuned regime that has received negligible prior attention -- reveal wide operating windows that support controlled-Z (CZ) fidelities >99.6%. Leveraging these windows, we design lattice architectures containing >1000 qubits, showing that even under 0.25% fabrication-induced frequency dispersion, the zero-collision yields in square and heavy-hexagonal lattices reach 80% and 100%, respectively. Thus, the siZZle-CZ gate is a scalable and collision-robust alternative to the CR gate, offering a viable route toward high-yield fixed-frequency transmon quantum processors.

Comments
23 pages, 14 figures

Related papers

Mitigation of quantum crosstalk in cross-resonance-based qubit architectures

Peng Zhao

The cross-resonance gate (cr gate) architecture that exploits fixed-frequency transmon qubits and fixed couplings is a leading candidate for quantum computing. Nonetheless, without the tunability of qubit parameters such as qubit frequencies and couplings, gate operations can be limited by the presence of quantum crosstalk arising from the always-on couplings. When increasing system sizes, this can become even more serious, considering frequency collisions caused by fabrication uncertainties. Here, we introduce a cr-gate-based transmon architecture with passive mitigation of both quantum crosstalk and frequency collisions. Assuming typical parameters, we show that $ZZ$ crosstalk can be suppressed while maintaining $XY$ couplings to support fast, high-fidelity cr gates. The architecture also allows one to go beyond the existing literature by extending the operating regions in which fast, high-fidelity cr gates are possible, thus alleviating the frequency-collision issue. To examine the practicality, we analyze the cr-gate performance in multiqubit lattices and provide an intuitive model for identifying and mitigating the dominant source of error. For the state-of-the-art precision in setting frequencies, we further investigate its impact on the gates. We find that $ZZ$ crosstalk and frequency collisions can be largely mitigated for neighboring qubits, while interactions beyond near-neighbor qubits can introduce new frequency collisions. As the strength is typically at the submegahertz level, adding weak off-resonant drives to selectively shift qubits can mitigate the collisions. This work could be useful for suppressing quantum crosstalk and improving gate fidelities in large-scale quantum processors based on fixed-frequency qubits and fixed couplings.

arXiv:2307.09995•Physical Review Applied•Nov 15, 2023•13 citations

Lattice patch structure for fixed-frequency transmon quantum computer with high-fidelity CNOT gates

Chanpyo Kim, Jeongsoo Kang, Younghun Kwon

Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code.To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler.This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability.Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual $R_z$ gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.

quant-pharXiv:2606.27017•Jun 26, 2026•0 citations

Lattice Patch Structure for Fixed-Frequency Transmon Quantum Computer with High-Fidelity CNOT Gates

Chanpyo Kim, Jeongsoo Kang, Younghun Kwon

Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code. To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler. This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability. Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual Rz gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.

Entropy•Jun 30, 2026•0 citations

Systematic frequency-collision analysis of the cross-resonance gate outside the straddling regime

Shinichi Inoue, Shotaro Shirai, Shuhei Tamate +4 more

Frequency crowding remains a major obstacle to scaling fixed-frequency transmon processors. Among the widely used all-microwave two-qubit gates, the cross-resonance (CR) gate is particularly sensitive to qubit-frequency spread because the conventional straddling regime condition constrains assignable qubit frequencies tightly and makes the system susceptible to frequency collisions. Here, we propose and analyze the CR gate outside the straddling regime, which we refer to as the far-detuned regime, and evaluate frequency collisions using a numerical method that remains accurate under high-intensity, smoothly ramped microwave drives. Based on this analysis, we perform systematic parameter sweeps and provide collision-free conditions that define designable frequency regions in which qubit frequencies can be assigned consistently with surrounding qubit frequencies. Furthermore, we formulate frequency allocation as a linear programming optimization on a unit-cell lattice with periodic boundary conditions to obtain an optimal allocation. We demonstrate that far-detuned designs significantly reduce collisions compared with designs in the straddling regime. Monte Carlo yield analysis indicates that 10% collision-free yield for a 1024-qubit square lattice at a 0.1% two-qubit-gate error threshold requires $σ_{\mathrm{f}}/2π\le 6.8~\mathrm{MHz}$. Our findings suggest that this is feasible with an approximately twofold reduction in the state-of-the-art qubit-frequency spread.

quant-pharXiv:2605.07868•May 11, 2026•0 citations

Fast ZZ-Free Entangling Gates for Superconducting Qubits Assisted by a Driven Resonator

Ziwen Huang, Tae-Yoon Kim, Tanay Roy +4 more

Engineering high-fidelity two-qubit gates is an indispensable step toward practical quantum computing. For superconducting quantum platforms, one important setback is the stray interaction between qubits, which causes significant coherent errors. For transmon qubits, protocols for mitigating such errors usually involve fine-tuning the hardware parameters or introducing usually noisy flux-tunable couplers. In this work, we propose a simple scheme to cancel these stray interactions. The coupler used for such cancellation is a driven high-coherence resonator, where the amplitude and frequency of the drive serve as control knobs. Through the resonator-induced-phase (RIP) interaction, the static ZZ coupling can be entirely neutralized. We numerically show that such a scheme can enable short and high-fidelity entangling gates, including cross-resonance CNOT gates within 40 ns and adiabatic CZ gates within 140 ns. Our architecture is not only ZZ free but also contains no extra noisy components, such that it preserves the coherence times of fixed-frequency transmon qubits. With the state-of-the-art coherence times, the error of our cross-resonance CNOT gate can be reduced to below 1e-4.

arXiv:2311.01332•Nov 2, 2023•0 citations

Hybrid Coupling Topology with Dynamic ZZ Suppression for Optimizing Circuit Depth during Runtime in Superconducting Quantum Processor

Uday Sannigrahi, Amlan Chakrabarti, Swapnil Saha +1 more

To reduce circuit depth when executing Quantum algorithms, it is necessary to maximize qubit connectivity on a near-term quantum processor. While addressing this, we also need to ensure high gate fidelity, suppression of unwanted ZZ cross-talk, a compact layout footprint, and minimal control hardware complexity to support scalability. In current superconducting quantum chips, fixed coupling is used as it is easier to scale, but it is limited by unwanted static ZZ interaction during single qubit operations, which degrades system performance. To overcome these challenges, we have introduced a first-of-its-kind hybrid tunable-coupling architecture that connects four fixed-frequency transmon qubits using a single coupler. This hybrid coupler uses off-resonant Stark drives to tune ZZ strength between qubit pairs. Experimentally backed simulation results indicate that our proposed hybrid design maximizes the qubit connectivity while reducing control overhead. This design achieves a near 20% reduction in circuit depth compared to IBM's Heavy-Hexagonal layout, showing its potential for scalability.

quant-pharXiv:2602.06812•Feb 9, 2026•0 citations
Fixed-frequency transmon qubits, characterized by simple architectures and long coherence times, are promising platforms for large-scale quantum computing. However, the rapidly increasing frequency collisions, which directly reduce the fabrication yield, hinder scaling, especially in cross-resonance (CR) gate-based architectures, wherein the restricted drive frequency severely limits the available design space. We investigate the Stark-induced ZZ by level excursions (siZZle) gate, which relaxes this limitation by allowing arbitrary drive-frequency choices. Extensive numerical analyses across a broad parameter range -- including the far-detuned regime that has received negligible prior attention -- reveal wide operating windows that support controlled-Z (CZ) fidelities >99.6%. Leveraging these windows, we design lattice architectures containing >1000 qubits, showing that even under 0.25% fabrication-induced frequency dispersion, the zero-collision yields in square and heavy-hexagonal lattices reach 80% and 100%, respectively. Thus, the siZZle-CZ gate is a scalable and collision-robust alternative to the CR gate, offering a viable route toward high-yield fixed-frequency transmon quantum processors.
The cross-resonance gate (cr gate) architecture that exploits fixed-frequency transmon qubits and fixed couplings is a leading candidate for quantum computing. Nonetheless, without the tunability of qubit parameters such as qubit frequencies and couplings, gate operations can be limited by the presence of quantum crosstalk arising from the always-on couplings. When increasing system sizes, this can become even more serious, considering frequency collisions caused by fabrication uncertainties. Here, we introduce a cr-gate-based transmon architecture with passive mitigation of both quantum crosstalk and frequency collisions. Assuming typical parameters, we show that ZZZZZZ crosstalk can be suppressed while maintaining XYXYXY couplings to support fast, high-fidelity cr gates. The architecture also allows one to go beyond the existing literature by extending the operating regions in which fast, high-fidelity cr gates are possible, thus alleviating the frequency-collision issue. To examine the practicality, we analyze the cr-gate performance in multiqubit lattices and provide an intuitive model for identifying and mitigating the dominant source of error. For the state-of-the-art precision in setting frequencies, we further investigate its impact on the gates. We find that ZZZZZZ crosstalk and frequency collisions can be largely mitigated for neighboring qubits, while interactions beyond near-neighbor qubits can introduce new frequency collisions. As the strength is typically at the submegahertz level, adding weak off-resonant drives to selectively shift qubits can mitigate the collisions. This work could be useful for suppressing quantum crosstalk and improving gate fidelities in large-scale quantum processors based on fixed-frequency qubits and fixed couplings.
Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code.To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler.This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability.Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual RzR_zRz​ gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.
Superconducting transmon processors represent a leading platform for large-scale quantum computing due to their high gate fidelities and scalability. However, conventional qubit-coupler-qubit (QCQ) architectures face critical physical and structural bottlenecks, notably frequency crowding [spectator qubit collisions] during system scaling and inefficient mapping onto the standard surface code. To overcome these limitations, we propose a novel lattice-patch architecture that couples four fixed-frequency transmons to a single fixed-frequency coupler. This design enhances qubit connectivity and maps directly onto the surface-code lattice unit [plaquette], thereby minimizing the compilation overhead associated with logical qubit implementation. Furthermore, utilizing an entirely fixed-frequency design intrinsically eliminates susceptibility to external flux noise, ensuring robust operational stability. Multi-level numerical simulations demonstrate CNOT gate fidelities exceeding 0.98 across all six connectivity directions within the patch. Nevertheless, the complex interaction network of the four-qubit architecture induces unintended residual phase accumulation during cross-resonance driving. This parasitic effect necessitates precise calibration, achievable via virtual Rz gates [software phase updates]. Ultimately, our results establish the lattice-patch architecture as an efficient, robust building block for future fault-tolerant quantum computers.
Frequency crowding remains a major obstacle to scaling fixed-frequency transmon processors. Among the widely used all-microwave two-qubit gates, the cross-resonance (CR) gate is particularly sensitive to qubit-frequency spread because the conventional straddling regime condition constrains assignable qubit frequencies tightly and makes the system susceptible to frequency collisions. Here, we propose and analyze the CR gate outside the straddling regime, which we refer to as the far-detuned regime, and evaluate frequency collisions using a numerical method that remains accurate under high-intensity, smoothly ramped microwave drives. Based on this analysis, we perform systematic parameter sweeps and provide collision-free conditions that define designable frequency regions in which qubit frequencies can be assigned consistently with surrounding qubit frequencies. Furthermore, we formulate frequency allocation as a linear programming optimization on a unit-cell lattice with periodic boundary conditions to obtain an optimal allocation. We demonstrate that far-detuned designs significantly reduce collisions compared with designs in the straddling regime. Monte Carlo yield analysis indicates that 10% collision-free yield for a 1024-qubit square lattice at a 0.1% two-qubit-gate error threshold requires σf/2π≤6.8 MHzσ_{\mathrm{f}}/2π\le 6.8~\mathrm{MHz}σf​/2π≤6.8 MHz. Our findings suggest that this is feasible with an approximately twofold reduction in the state-of-the-art qubit-frequency spread.
Engineering high-fidelity two-qubit gates is an indispensable step toward practical quantum computing. For superconducting quantum platforms, one important setback is the stray interaction between qubits, which causes significant coherent errors. For transmon qubits, protocols for mitigating such errors usually involve fine-tuning the hardware parameters or introducing usually noisy flux-tunable couplers. In this work, we propose a simple scheme to cancel these stray interactions. The coupler used for such cancellation is a driven high-coherence resonator, where the amplitude and frequency of the drive serve as control knobs. Through the resonator-induced-phase (RIP) interaction, the static ZZ coupling can be entirely neutralized. We numerically show that such a scheme can enable short and high-fidelity entangling gates, including cross-resonance CNOT gates within 40 ns and adiabatic CZ gates within 140 ns. Our architecture is not only ZZ free but also contains no extra noisy components, such that it preserves the coherence times of fixed-frequency transmon qubits. With the state-of-the-art coherence times, the error of our cross-resonance CNOT gate can be reduced to below 1e-4.
To reduce circuit depth when executing Quantum algorithms, it is necessary to maximize qubit connectivity on a near-term quantum processor. While addressing this, we also need to ensure high gate fidelity, suppression of unwanted ZZ cross-talk, a compact layout footprint, and minimal control hardware complexity to support scalability. In current superconducting quantum chips, fixed coupling is used as it is easier to scale, but it is limited by unwanted static ZZ interaction during single qubit operations, which degrades system performance. To overcome these challenges, we have introduced a first-of-its-kind hybrid tunable-coupling architecture that connects four fixed-frequency transmon qubits using a single coupler. This hybrid coupler uses off-resonant Stark drives to tune ZZ strength between qubit pairs. Experimentally backed simulation results indicate that our proposed hybrid design maximizes the qubit connectivity while reducing control overhead. This design achieves a near 20% reduction in circuit depth compared to IBM's Heavy-Hexagonal layout, showing its potential for scalability.