The scalability of quantum computing in supporting sophisticated algorithms critically depends not only on qubit quality and error handling, but also on the efficiency of classical control, constrained by the cryogenic control bandwidth and energy budget. In this work, we address this challenge by investigating the algorithmic complexity of quantum circuits at the instruction set architecture (ISA) level. We introduce an energy-efficient quantum instruction set architecture (EQISA) that synthesizes quantum circuits in a discrete Solovay-Kitaev basis of fixed depth and encodes instruction streams using a sparse dictionary learned from decomposing a set of Haar-random unitaries, followed by entropy-optimal Huffman coding and an additional lossless bzip2 compression stage. This approach is evaluated on benchmark quantum circuits demonstrating over 60% compression of quantum instruction streams across system sizes, enabling proportional reductions in classical control energy and communication overhead without loss of computational fidelity. Beyond compression, EQISA facilitates the discovery of higher-level composable abstractions in quantum circuits and provides estimates of quantum algorithmic complexity. These findings position EQISA as an impactful direction for improving the energy efficiency and scalability of quantum control architectures.
The scalability of quantum computing in supporting sophisticated algorithms critically depends not only on qubit quality and error handling, but also on the efficiency of classical control, constrained by the cryogenic control bandwidth and energy budget. In this work, we address this challenge by investigating the algorithmic complexity of quantum circuits at the instruction set architecture (ISA) level. We introduce an energy-efficient quantum instruction set architecture (EQISA) that synthesizes quantum circuits in a discrete Solovay-Kitaev basis of fixed depth and encodes instruction streams using a sparse dictionary learned from decomposing a set of Haar-random unitaries, followed by entropy-optimal Huffman coding and an additional lossless bzip2 compression stage. This approach is evaluated on benchmark quantum circuits demonstrating over 60% compression of quantum instruction streams across system sizes, enabling proportional reductions in classical control energy and communication overhead without loss of computational fidelity. Beyond compression, EQISA facilitates the discovery of higher-level composable abstractions in quantum circuits and provides estimates of quantum algorithmic complexity. These findings position EQISA as an impactful direction for improving the energy efficiency and scalability of quantum control architectures.
Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.
Continuing the scaling of quantum computers hinges on building classical control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the control processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O(102) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.
Execution of quantum algorithms requires a quantum computer architecture with a dedicated quantum instruction set that is capable of supporting translation of workloads into actual quantum operations acting on the qubits. State-of-the-art qubit control setups typically utilize general purpose test instruments such as arbitrary waveform generators (AWGs) to generate a limited set of waveforms or pulses. These waveforms are precomputed and stored prior to execution, and then used to produce control pulses during execution. Besides their prohibitive cost and limited scalability, such instruments suffer from poor programmability due to the absence of an instruction set architecture (ISA). Limited memory for pulse storage ultimately determines the total number of supported quantum operations. In this work, we present a scalable qubit control system that enables efficient qubit control using a flexible ISA to drive a direct digital synthesis (DDS) pipeline producing nanosecond-accurate qubit control signals dynamically. The designed qubit controller provides a higher density of control channels, a scalable design, better programmability, and lower cost compared to state-of-the-art systems. In this work, we discuss the new qubit controller's capabilities, its architecture and instruction set, and present experimental results for coherent qubit control.
Quantum computing promises an effective way to solve targeted problems that are classically intractable. Among them, quantum computers built with superconducting qubits are considered one of the most advanced technologies, but they suffer from short coherence times. This can get exaggerated when they are controlled directly by general-purpose host machines, which in turn leads to the loss of quantum information. To mitigate this, we need quantum control processors (QCPs) positioned between quantum processing units (QPUs) and host machines to reduce latencies. However, existing QCPs are built on top of designs with no or inefficient scalability, requiring a large number of instructions when scaling to more qubits. In addition, interactions between current QCPs and host machines require frequent data transmissions and offline computations to obtain final results from hundreds of repeated executions, which limits the performance of quantum computers.In this paper, we propose a QCP — called HiSEP-Q — featuring a novel quantum instruction set architecture (QISA) and its microarchitecture implementation. For efficient control, we utilize mixed-type addressing modes and mixed-length instructions in HiSEP-Q, which provides an efficient way to concurrently address more than 100 qubits. Further, for efficient read-out and analysis, we develop a novel onboard accumulation and sorting unit, which eliminates the data transmission of raw data between the QCPs and host machines and enables real-time result processing. Compared to the state-of-the-art, our proposed QISA achieves at least 62% and 28% improvements in encoding efficiency with real and synthetic quantum circuits, respectively. We also validate the microarchitecture on a field-programmable gate array (FPGA), which exhibits low power and resource consumption, even as the number of qubits scales to 100. Both hardware and ISA evaluations demonstrate that HiSEP-Q features high scalability and efficiency toward the number of controlled qubits.
A widely-used quantum programming paradigm comprises of both the data How and control How. Existing quantum hardware cannot well support the control How, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are either too high-level or too restricted to support comprehensive How control on the hardware. Also, as observed with the quantum microinstruction set QuMIS [1], the quantum instruction set architecture (QISA) design may suffer from limited scalability and Hexibility because of microarchitectural constraints. It is an open challenge to design a scalable and Hexible QISA which provides a comprehensive abstraction of the quantum hardware. In this paper, we propose an executable QISA, called eQASM, that can be translated from quantum assembly language (QASM), supports comprehensive quantum program How control, and is executed on a quantum control microarchitecture. With efficient timing specification, single-operation-multiple-qubit execution, and a very-long-instruction-word architecture, eQASM presents better scalability than QuMIS. The definition of eQASM focuses on the assembly level to be expressive. Quantum operations are configured at compile time instead of being defined at QISA design time. We instantiate eQASM into a 32-bit instruction set targeting a seven-qubit superconducting quantum processor. We validate our design by performing several experiments on a two-qubit quantum processor.
Convolution operations are foundational to classical image processing and modern deep learning architectures, yet their extension into the quantum domain has remained algorithmically and physically costly due to inefficient data encoding and prohibitive circuit complexity. In this work, we present a resource-efficient quantum algorithm that reformulates the convolution product as a structured matrix multiplication via a novel sparse reshaping formalism. Leveraging the observation that localized convolutions can be encoded as doubly block-Toeplitz matrix multiplications, we construct a quantum framework wherein sparse input patches are prepared using optimized key-value QRAM state encoding, while convolutional filters are represented as quantum states in superposition. The convolution outputs are computed through inner product estimation using a low-depth SWAP test circuit, which yields probabilistic amplitude information with reduced sampling overhead. Our architecture supports batched convolution across multiple filters using a generalized SWAP circuit. Compared to prior quantum convolutional approaches, our method eliminates redundant preparation costs, scales logarithmically with input size under sparsity, and enables direct integration into hybrid quantum-classical machine learning pipelines. This work provides a scalable and physically realizable pathway toward quantum-enhanced feature extraction, opening up new possibilities for quantum convolutional neural networks and data-driven quantum inference.