We present EmuPlat, a framework-agnostic quantum hardware emulation platform that addresses the interoperability gap between high-level quantum programming frameworks and hardware-specific pulse control systems. Unlike existing solutions that operate within isolated software stacks, EmuPlat provides a unified infrastructure with an extensible architecture that supports multiple quantum computing frameworks through its adapter pattern design, and its current implementation demonstrates CUDA-Q integration via OpenQASM translation. The platform implements a complete transpiler-compiler pipeline that systematically transforms abstract quantum circuits through four validated stages: (1) recursive gate decomposition to a minimal native set \(\mathcal {G}_{\text{native}} = \lbrace I, Z, RZ(\theta),\text{GPI2}(\phi),\\ CZ, M\rbrace\), (2) virtual Z optimization implementing phase tracking without physical pulses, (3) connectivity-aware routing with automated SWAP insertion, and (4) deterministic pulse compilation respecting hardware timing constraints. Our modular architecture, based on clean architecture principles and featuring a novel adapter pattern, supports the extensible integration of multiple quantum dynamics simulation engines while maintaining consistent interfaces. We demonstrate EmuPlat’s capabilities through comprehensive benchmarks on superconducting transmon architectures: Bell-state preparation achieves high fidelity (>99.9%) with hardware-calibrated noise models, while 4-qubit Quantum Fourier Transform implementations validate the pipeline for moderately sized quantum systems. Virtual Z optimisation achieves an average 41% reduction in pulse count for phase-heavy algorithms. Compilation overhead analysis shows a total pipeline latency of 5-12ms, with framework translation accounting for 66-88% of the overhead. The platform’s production-ready implementation, validated through end-to-end testing with TransformationValidator, establishes EmuPlat as essential infrastructure for accelerating hybrid quantum-classical algorithm development and hardware-software co-design.
We present EmuPlat, a framework-agnostic quantum hardware emulation platform that addresses the interoperability gap between high-level quantum programming frameworks and hardware-specific pulse control systems. Unlike existing solutions that operate within isolated software stacks, EmuPlat provides a unified infrastructure with an extensible architecture that supports multiple quantum computing frameworks through its adapter pattern design, and its current implementation demonstrates CUDA-Q integration via OpenQASM translation. The platform implements a complete transpiler-compiler pipeline that systematically transforms abstract quantum circuits through four validated stages: (1) recursive gate decomposition to a minimal native set (\mathcal {G}_{\text{native}} = \lbrace I, Z, RZ(\theta),\text{GPI2}(\phi),\ CZ, M\rbrace), (2) virtual Z optimization implementing phase tracking without physical pulses, (3) connectivity-aware routing with automated SWAP insertion, and (4) deterministic pulse compilation respecting hardware timing constraints. Our modular architecture, based on clean architecture principles and featuring a novel adapter pattern, supports the extensible integration of multiple quantum dynamics simulation engines while maintaining consistent interfaces. We demonstrate EmuPlat’s capabilities through comprehensive benchmarks on superconducting transmon architectures: Bell-state preparation achieves high fidelity (>99.9%) with hardware-calibrated noise models, while 4-qubit Quantum Fourier Transform implementations validate the pipeline for moderately sized quantum systems. Virtual Z optimisation achieves an average 41% reduction in pulse count for phase-heavy algorithms. Compilation overhead analysis shows a total pipeline latency of 5-12ms, with framework translation accounting for 66-88% of the overhead. The platform’s production-ready implementation, validated through end-to-end testing with TransformationValidator, establishes EmuPlat as essential infrastructure for accelerating hybrid quantum-classical algorithm development and hardware-software co-design.
Quantum computing holds transformative potential, but its adoption is hindered by the complexity of generating efficient, hardware-specific code. This work presents a modular, extensible compiler framework that bridges high-level quantum languages with diverse hardware architectures. The framework consists of three modules: a front-end for parsing quantum code into a hardware-agnostic intermediate representation (IR), an optimization module for enhancing quantum circuits through gate synthesis, qubit routing, and error mitigation, and a back-end for generating hardware-specific instructions. Major contributions include a hardware-agnostic IR for cross-platform compatibility, optimization techniques to reduce gate complexity and noise, and hardware-specific adaptations to improve execution fidelity. A practical demonstration optimizes quantum circuits, highlighting the impact of hardware constraints. Comparative analysis of IBM Quantum and IonQ platforms underscores the role of qubit connectivity and noise resilience in algorithmic performance. This scalable framework enhances quantum software development and efficient hardware utilization.
QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.
QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 10× faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA. Source code: http://github.com/pnnl/qasmtrans
We present a platform-agnostic modular architecture that addresses the increasingly fragmented landscape of quantum computing benchmarking by decoupling problem generation, circuit execution, and results analysis into independent, interoperable components. Supporting over 20 benchmark variants ranging from simple algorithmic tests like Bernstein-Vazirani to complex Hamiltonian simulation with observable calculations, the system integrates with multiple circuit generation APIs (Qiskit, CUDA-Q, Cirq) and enables diverse workflows. We validate the architecture through successful integration with Sandia's pyGSTi for advanced circuit analysis and CUDA-Q for multi-GPU HPC simulations. Extensibility of the system is demonstrated by implementing dynamic circuit variants of existing benchmarks and a new quantum reinforcement learning benchmark, which become readily available across multiple execution and analysis modes. Our primary contribution is identifying and formalizing modular interfaces that enable interoperability between incompatible benchmarking frameworks, demonstrating that standardized interfaces reduce ecosystem fragmentation while preserving optimization flexibility. This architecture has been developed as a key enhancement to the continually evolving QED-C Application-Oriented Performance Benchmarks for Quantum Computing suite.
As quantum computing systems continue to scale up and become more clustered, efficiently compiling user quantum programs into high-fidelity executable sequences on real hardware remains a key challenge for current quantum compilation systems. In this study, we introduce a system-software framework that integrates resource virtualization and hardware-aware compilation for real quantum computing processors, termed QSteed. QSteed virtualizes quantum processors through a 4-layer abstraction hierarchy comprising the real quantum processing unit (QPU), standard QPU (StdQPU), substructure of the QPU (SubQPU), and virtual QPU (VQPU). These abstractions, together with calibration data, device topology, and noise descriptors, are maintained in a dedicated database to enable unified and fine-grained management across superconducting quantum platforms. At run time, the modular compiler queries the database to match each incoming circuit with the most suitable VQPU, after which it confines layout, routing, gate resynthesis, and noise-adaptive optimizations to that virtual subregion. The complete stack has been deployed on the Quafu superconducting cluster, where experimental runs confirm the correctness of the virtualization model and the efficacy of the compiler without requiring modifications to user code. By integrating resource virtualization with a select-then-compile workflow, QSteed demonstrates a robust architecture for compiling programs on noisy superconducting processors. This architectural approach offers a promising path toward efficient compilation needs across various superconducting quantum computing platforms in the noisy intermediate-scale quantum era.
This work presents a portable, modular quantumcircuit emulator designed to accelerate algorithm prototyping by leveraging Central Processing Unit (CPU) and Compute Unified Device Architecture (CUDA)-enabled Graphic Processing Unit (GPU) backends for dense linearalgebra workloads.The emulator provides a lightweight backend abstraction that unifies NumPy and CuPy, supports both statevector and density-matrix representations, and implements efficient multi-target unitary embedding and Kraus-map noise channels.These capabilities enable rapid exploration of quantum algorithms that require full 2 n × 2 n operators, such as quantum phase estimation, full Quantum Fourier Transform (QFT), and noise-aware variational circuits, while minimizing host/device transfer and preserving numerical parity between backends.Implementation strategies are described for embedding single-and multi-qubit gates, parameterized rotations, and controlled unitaries, along with an "apply_unitary_on_targets" routine that employs reshape/matrix-multiply/reshape patterns to map arbitrary target sets to dense GPU kernels for high throughput.Using a curated benchmark suite of dense quantum workloads and microbenchmarks, including large matrix multiplies and Fast Fourier Transforms (FFT), performance is quantified across a range of qubit counts and precisions.The results demonstrate substantial speedups on modern NVIDIA GPUs for workloads dominated by dense linear algebra, identify cross-over points where GPU acceleration becomes beneficial, and analyse memory/precision trade-offs for complex64 versus complex128.The presented emulator lowers the barrier for noise-aware algorithm prototyping by combining practical software ergonomics with GPU performance, enabling faster iteration on algorithm design and noise-mitigation strategies on commodity single-node hardware.While the abstraction layer ensures portability, achieving peak performance currently requires hardwarespecific tuning-a limitation we address through future automation strategies.