Quantum algorithms face significant challenges due to qubit susceptibility to environmental noise, and quantum error correction typically requires prohibitive resource overhead. This paper proposes that quantum algorithms may possess inherent noise resilience characteristics that could reduce implementation barriers. We investigate Shor's algorithm by applying circuit-level noise models directly to the original algorithm circuit. Our findings reveal that Shor's algorithm demonstrates superior fault tolerance under Z noise compared to X and Y noise. Focusing on the modular exponentiation circuit which is the core component of the algorithm, we conduct fault-tolerant position statistics on circuits with bit lengths from 4 to 9. The results show that under Z noise, fault-tolerant positions grow with the same quartic polynomial order as potential error positions as the problem scale increases. In contrast, fault tolerance under X and Y noise exhibits a strong dependence on the composite number N and the parameter a. Based on these findings, we develop an extrapolation method predicting that the minimum probability of a correct output of the modular exponentiation circuit to factor 2048 bit integers under biased noise is approximately 1.417*{10}^{-17}.
Quantum algorithms face significant challenges due to qubit susceptibility to environmental noise, and quantum error correction typically requires prohibitive resource overhead. This paper proposes that quantum algorithms may possess inherent noise resilience characteristics that could reduce implementation barriers. We investigate Shor's algorithm by applying circuit-level noise models directly to the original algorithm circuit. Our findings reveal that Shor's algorithm demonstrates superior fault tolerance under Z noise compared to X and Y noise. Focusing on the modular exponentiation circuit which is the core component of the algorithm, we conduct fault-tolerant position statistics on circuits with bit lengths from 4 to 9. The results show that under Z noise, fault-tolerant positions grow with the same quartic polynomial order as potential error positions as the problem scale increases. In contrast, fault tolerance under X and Y noise exhibits a strong dependence on the composite number N and the parameter a. Based on these findings, we develop an extrapolation method predicting that the minimum probability of a correct output of the modular exponentiation circuit to factor 2048 bit integers under biased noise is approximately 1.417*{10}^{-17}.
Quantum computing promises revolutionary advances in cryptography, particularly through Shor's algorithm, which can factor large integers in polynomial time and threaten traditional RSA encryption. Through simulation experiments, our research compares Shor's algorithm implementation in ideal versus noisy quantum environments. Under ideal conditions, we factored semiprimes up to N=299 with reasonable resources, but with noise introduction, this ceiling dropped to approximately N=95, beyond which computational costs increased exponentially. The performance gap is striking: ideal simulations factored N=91 in 4 seconds, while noisy simulations required 2,600 seconds—a 650-fold increase. Our hybrid quantum-classical approach showed that noise simulation required modified circuit architectures, reducing gate count growth from 50 to 42.5 gates for comparable test numbers. Qubit requirements followed a step-function pattern in both environments, scaling from 12 qubits for N=15 to 21 qubits for N=91-95, while circuit depth increased from 11 to 17-19 units, with slightly shallower circuits in noisy conditions. In our paper, we propose a hybrid implementation strategy that addresses hardware limitations, present empirical findings on the impact of quantum noise on factoring efficiency, and evaluate the cryptographic security implications under realistic conditions. Our findings underscore the need for fault-tolerant quantum computing and error correction, especially as optimizations suggest factoring 2048-bit RSA keys would require approximately 20 million qubits running for 8 hours. This highlights the urgency in transitioning to post-quantum cryptographic algorithms like CRYSTALS-Dilithium and CRYSTALS-Kyber being standardized by NIST.
This experimental study introduces a hybrid quantum-classical framework aiming to improve the noise robustness of Shor’s algorithm. By incorporating a novel hybrid logic gate into the modular exponentiation phase, the framework stabilizes qubit interactions and decreases decoherence in a noisy environment simulated by IBM Qiskit. Performance evaluation is accomplished by fidelity and entropy analysis across varied noise levels. Comparative benchmarking with conventional techniques, including Shor’s code, Bacon-Shor code, dynamical decoupling, and zero noise extrapolation, demonstrates that the proposed hybrid gate achieves higher fidelity (0.90) and lower entropy (0.33), while preserving minimal resource overhead. These findings highlight the framework’s effectiveness as a hardware-independent, scalable solution for Noisy Intermediate-Scale Quantum (NISQ) devices. Instead, the study offers an approach toward a scalable, error-resilient model to avoid exaggerating scalability. Despite its promising outcomes, study is presently limited to simulations and a single noise model. Future work will explore implementation on real quantum hardware and extend the framework to incorporate a broader range of noise profiles, contributing to the evolution of fault-tolerant quantum computation.
The publication in 1994 of Shor's algorithm, which allows factorisation of composite number N in a time polynomial in its binary length L has been the primary catalyst for the race to construct a functional quantum computer. However, it seems clear that any practical system that may be developed will not be able to perform completely error free quantum gate operations or shield even idle qubits from inevitable error effects. Hence, the practicality of quantum algorithms needs to be investigated to not only determine limitations on such algorithms in a noisy quantum computer, but also to estimate what demands must be made of quantum error correction (QEC). Shor's algorithm is a combination of both classical pre and post-processing, and also a quantum period finding subroutine (QPF) which allows for the exponential speed up of this algorithm on a quantum device. This paper will look at the stability of this quantum subroutine under the effects of several error models. Direct simulation of the entire QPF subroutine required to factorise a given composite number N in the presence of errors shows that the circuit required to implement Shor's algorithm is very sensitive to a small number of errors within the entire calculation. Well designed and efficient error correction codes, quick gate times and very low gate error rates will be essential for any physical realisation of Shor's factoring algorithm.
Due to very high projected error rates, large scale quantum computers will require substantial fault tolerance just to maintain a minimum level of reliability. We present tools to better analyze the performance of large, fault tolerant quantum computer designs. We find that current uses of quantum error correction are overly conservative in mitigating the impact of gate errors and negligent of other error sources in quantum data communication and memory.
We have developed circuit layout heuristics to generate detailed designs in trapped ion quantum computing technology. From these designs, we can extract much more accurate error models for a given application, including all gate, movement and idle errors on qubits. Using these extracted models, our flexible error simulation environment determines the overall failure probability of the design. Included in this simulation environment is a bit-parallel Monte Carlo technique that is 10 times faster than previous fault propagation simulations. This allows us to evaluate the reliability of designs that are an order of magnitude larger, in the same amount of time.
Using this analysis framework to verify reliability, we have developed a linear programming-based optimization for error correction which decreases overall circuit resources by an order of magnitude. In some cases, our optimization actually improves overall system reliability by removing error correction. We combine this optimization with judicious quantum error correcting code selection to provide efficient designs for large quantum arithmetic kernels used in Shor's factorization algorithm. We show our optimized designs perform 2x to 100x better than previous works in terms of probabilistic area-delay product. Additionally, the area of our layout of a 1024-bit factoring using Shor's algorithm is 64cm2, a substantial improvement compared to the 0.9m2 state-of-the-art design from prior work. A design size reduction by this amount will make fabricating such an application feasible much sooner.
Quantum error correction (QEC) is essential for realizing scalable quantum computation. However, when evaluating its benefits, most analyses assume idealized components, overlooking the imperfections inherent in realistic fault-tolerant (FT) implementations. In this paper, we investigate the performance of QEC schemes taking into account that quantum gates and measurements are themselves error-prone. We derive bounds for the failure probability of Shor-style FT-QEC schemes using limited structural information, such as the number of flag qubits and quantum gates. Our analysis separates and quantifies two key contributors to the failure rate: decoding errors and residual errors arising from circuit-level faults. The derived bounds highlight fundamental limitations in Shor-style FT-QEC performance and quantify how circuit imperfections degrade error correction capabilities, under the assumption of depolarizing noise.
We provide two improvements to Regev's recent quantum factoring algorithm (Journal of the ACM 2025), addressing its space efficiency and its noise-tolerance. Our first contribution is to improve the quantum space efficiency of Regev's algorithm while keeping the circuit size the same. Our main result constructs a quantum factoring circuit using O(nlogn) qubits and O(n3/2logn) gates. We achieve the best of Shor and Regev (upto a logarithmic factor in the space complexity): on the one hand, Regev's circuit requires O(n3/2) qubits and O(n3/2logn) gates, while Shor's circuit requires O(n2logn) gates but only O(nlogn) qubits. As with Regev, to factor an n-bit integer N, we run our circuit independently O(n) times and apply Regev's classical postprocessing procedure. Our optimization is achieved by implementing efficient and reversible exponentiation with Fibonacci numbers in the exponent, rather than the usual powers of 2, adapting work by Kaliski (arXiv:1711.02491) from the classical reversible setting to the quantum setting. This technique also allows us to perform quantum modular exponentiation that is efficient in both space and size without requiring significant precomputation, a result that may be useful for other quantum algorithms. A key ingredient of our exponentiation implementation is an efficient circuit for a function resembling in-place quantum-quantum modular multiplication. Our second contribution is to show that Regev's classical postprocessing procedure can be modified to tolerate a constant fraction of the quantum circuit runs being corrupted by errors. In contrast, Regev's analysis of his classical postprocessing procedure requires all ≈n runs to be successful. In a nutshell, we achieve this using lattice reduction techniques to detect and filter out corrupt samples.