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arXiv:2506.20098

A Cost-Effective Layout-Aware Quantum Circuit Synthesis For Triangular, Square, and Heavy-Hex Layouts

Yang, Sonia, Ali Al-Bayaty, Marek A. Perkowski

Published Jun 25, 2025• 0 citations
arXivHTMLPDF

Abstract

The quantum layout and the mapping of logical to physical qubits are crucial in quantum circuit synthesis for a real quantum computer. Circuits that include large $n$-bit Toffoli gates ($n \geq 3$), such as those designed from cost-expensive gates and hard-to-decompose Exclusive-or Sum of Products (ESOP) expressions, have complications of effective mappings into contemporary quantum layouts, such as the square grid and heavy-hex layouts. These complications are primarily caused by the limited connectivity among the physical qubits in such layouts, leading to the insertion of many additional SWAP gates. This paper introduces a new quantum circuit synthesis methodology by exploring the advantage of a Positive Davio lattice (PDL) as an intermediate representation to create our proposed triangular layout and layout-aware circuits. From these circuits, we introduce and form the SWAT gate, composed of a SWAP gate followed by a 3-bit Toffoli gate. To illustrate the usefulness of our method for existing industrial quantum layouts, we also introduce cost-effective mappings of the resulting circuits onto square grid and heavy-hex layouts without additional SWAP gates. This is done with the help of the SWAT gate. Our research highlights PDLs as an efficient tool for layout-aware quantum circuit synthesis.

DOI
10.48550/arxiv.2506.20098

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The quantum layout and the mapping of logical to physical qubits are crucial in quantum circuit synthesis for a real quantum computer. Circuits that include large nnn-bit Toffoli gates (n≥3n \geq 3n≥3), such as those designed from cost-expensive gates and hard-to-decompose Exclusive-or Sum of Products (ESOP) expressions, have complications of effective mappings into contemporary quantum layouts, such as the square grid and heavy-hex layouts. These complications are primarily caused by the limited connectivity among the physical qubits in such layouts, leading to the insertion of many additional SWAP gates. This paper introduces a new quantum circuit synthesis methodology by exploring the advantage of a Positive Davio lattice (PDL) as an intermediate representation to create our proposed triangular layout and layout-aware circuits. From these circuits, we introduce and form the SWAT gate, composed of a SWAP gate followed by a 3-bit Toffoli gate. To illustrate the usefulness of our method for existing industrial quantum layouts, we also introduce cost-effective mappings of the resulting circuits onto square grid and heavy-hex layouts without additional SWAP gates. This is done with the help of the SWAT gate. Our research highlights PDLs as an efficient tool for layout-aware quantum circuit synthesis.
State-of-the-art studies on quantum layout synthesis have proposed various approaches based on the assumption that the input circuit is only composed of single-qubit and two-qubit gates. This assumption greatly simplifies the layout synthesis problem, and thus they only require ensuring that all controlled-NOT (CNOT) gates satisfy the hardware constraints imposed by a given coupling graph. However, during the design of quantum circuits, multi-controlled Toffoli (MCT) gates are usually used to better characterize the function of the circuits. Directly decomposing them into single and two-qubit gates with a fixed routine ignores the flexibility and optimization opportunity provided by various decomposition (i.e., logic synthesis) possibilities and thus suffers from sub-optimal results. This article proposes a co-optimization approach for quantum logic and layout synthesis. The MCT gates are first decomposed into Toffoli gates, and an efficient qubit mapping checking process is proposed to optimally solve the SWAP-free layout synthesis problem by automatically determining the decomposition result of each Toffoli gate. If a SWAP-free result cannot be found, the proposed algorithm flow is then used to obtain a solution that minimizes the total cost that simultaneously counts the cost caused by the different decomposition methods for Toffoli gates and the cost induced by SWAP gates. Compared with a state-of-the-art method, the proposed approach reduces the number of additional CNOT gates by 16% with around 25X runtime speedup for the cases with SWAP-free solutions, which cannot be obtained without the co-optimization approach.
In Layout Synthesis, the logical qubits of a quantum circuit are mapped to the physical qubits of a given quantum hardware platform, taking into account the connectivity of physical qubits. This involves inserting SWAP gates before an operation is applied on distant qubits. Optimal Layout Synthesis is crucial for practical Quantum Computing on current error-prone hardware: Minimizing the number of SWAP gates directly mitigates the error rates when running quantum circuits. In recent years, several approaches have been proposed for minimizing the required SWAP insertions. The proposed exact approaches can only scale to a small number of qubits. In this paper, we provide two encodings for Optimal Layout Synthesis as a classical planning problem. We use optimal classical planners to synthesize the optimal layout for a standard set of benchmarks. Our results show the scalability of our approach compared to previous leading approaches. We can optimally map circuits with 9 qubits onto a 14 qubit platform, which could not be handled before by exact methods.
In Layout Synthesis, the logical qubits of a quantum circuit are mapped to the physical qubits of a given quantum hardware platform, taking into account the connectivity of physical qubits. This involves inserting SWAP gates before an operation is applied on distant qubits. Optimal Layout Synthesis is crucial for practical Quantum Computing on current error-prone hardware: Minimizing the number of SWAP gates directly mitigates the error rates when running quantum circuits. In recent years, several approaches have been proposed for minimizing the required SWAP insertions. The proposed exact approaches can only scale to a small number of qubits. Proving that a number of swap insertions is optimal is much harder than producing near optimal mappings. In this paper, we provide two encodings for Optimal Layout Synthesis as a classical planning problem. We use optimal classical planners to synthesize the optimal layout for a standard set of benchmarks. Our results show the scalability of our approach compared to previous leading approaches. We can optimally map circuits with 9 qubits onto a 14 qubit platform, which could not be handled before by exact methods.
A cost-effective n-bit Toffoli gate is proposed to be realized (or transpiled) based on the layouts (linear, T-like, and I-like) and the number of n physical qubits for IBM quantum computers. This proposed gate is termed the "layout-aware n-bit Toffoli gate". The layout-aware n-bit Toffoli gate is designed using the visual approach of the Bloch sphere, from the visual representations of the rotational quantum operations for IBM native gates. In this paper, we also proposed a new formula for the quantum cost, which calculates the total number of native gates, the crossing connections, and the depth of the final transpiled quantum circuit. This formula is termed the "transpilation quantum cost". After transpilation, our proposed layout-aware n-bit Toffoli gate always has a much lower transpilation quantum cost than that of the conventional n-bit Toffoli gate, where 3 <= n <= 7 qubits, for different IBM quantum computers.
In recent years, the emergence of the Noisy Intermediate-Scale Quantum (NISQ) era has led to the development of a wide variety of quantum devices, marking a dynamic phase in the field of quantum computing. Despite these advancements, practical applications of quantum computers still face significant challenges, one of the most prominent being the limited connectivity between physical quantum bits (qubits). This limitation requires quantum circuits to be recompiled through layout synthesis before they can be executed on quantum devices. Layout synthesis determines the specific placement of quantum gates within the circuit on the physical hardware. When gates do not align with the connectivity constraints of the device, additional quantum gates must be inserted to remap the qubits, which can negatively affect the circuit’s efficiency and performance. To address this issue, the primary goal of this paper is to enhance the mapping process within layout synthesis, aiming to optimize both the layout and the circuit depth. Experimental results demonstrate that the proposed method effectively reduces the quantum circuit depth, outperforming other existing approaches in terms of efficiency.
Quantum computing has increasingly drawn interest and investments from the academic, industrial, and governmental research communities worldwide. Among quantum algorithms, Quantum Search is important for its quadratic speedup over its classical-computing counterpart. A key ingredient in its implementation is the Multi-Control Toffoli (MCT) gate, which creates a Boolean product of control variables and XORs it into the target. On an idealized quantum computer, all-to-all connectivity would eliminate the need to use SWAP gates to communicate information. This is, however, not affordable in the current Noisy Intermediate-Scale Quantum (NISQ) computing era. In this work, we discuss how to efficiently implement MCT gates on 2D Square Lattices (2DSL), suitable for superconducting circuits, by taking advantage of relative-phase Toffoli gates and H-tree layouts to drastically reduce resulting circuits' depths and the amount of SWAPping required.