Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2505.23567 · PRX Quantum

Scalable Decoding Protocols for Fast Transversal Logic in the Surface Code

Mark L. Turner, Earl T. Campbell, Ophelia Crawford, Neil I. Gillespie, Joan Camps

Published Dec 15, 2025• 2 citations
arXivHTMLPDF

Abstract

Atomic, molecular and optical (AMO) approaches to quantum computing are promising due to their increased connectivity, long coherence times and apparent scalability. However, they have a significantly reduced cadence of syndrome extraction compared to superconducting devices, a potentially crippling slow-down given the substantial logical gate counts required for quantum advantage. Transversal logic, which exploits higher connectivity, has the potential to significantly speed up the logical clock rate by reducing the number of syndrome extraction rounds required, but current decoders for fast transversal logic are not scalable. This is not just because existing decoders are too slow to handle the large decoding volumes resulting from fast logic; transversal logic breaks the key structural properties that make real-time decoding of lattice surgery efficient. We introduce two windowed decoding protocols for transversal logic in the surface code that restore modularity and locality to the decoding problem. Using our protocols, we show that, with a very small space overhead, our scalable decoders unlock an order of magnitude speedup for transversal logic compared to lattice surgery. Taken together, our results provide key evidence for the viability of large-scale algorithms on AMO qubits.

DOI
10.1103/nx6p-hjqy

Related papers

Fast correlated decoding of transversal logical algorithms

Madelyn Cain, Dolev Bluvstein, Chen Zhao +7 more

Quantum error correction (QEC) is required for large-scale computation, but incurs a significant resource overhead. Recent advances have shown that by jointly decoding logical qubits in algorithms composed of transversal gates, the number of syndrome extraction rounds can be reduced by a factor of the code distance $d$, at the cost of increased classical decoding complexity. Here, we reformulate the problem of decoding transversal circuits by directly decoding relevant logical operator products as they propagate through the circuit. This procedure transforms the decoding task into one closely resembling that of a single-qubit memory propagating through time. The resulting approach leads to fast decoding and reduced problem size while maintaining high performance. Focusing on the surface code, we prove that this method enables fault-tolerant decoding with minimum-weight perfect matching, and benchmark its performance on example circuits including magic state distillation. We find that the threshold is comparable to that of a single-qubit memory, and that the total decoding run time can be, in fact, less than that of conventional lattice surgery. Our approach enables fast correlated decoding, providing a pathway to directly extend single-qubit QEC techniques to transversal algorithms.

arXiv:2505.13587•May 19, 2025•1 citation

Correlated Decoding of Logical Algorithms with Transversal Gates

Madelyn Cain, Chen Zhao, Hengyun Zhou +5 more

Quantum error correction is believed to be essential for scalable quantum computation, but its implementation is challenging due to its considerable space-time overhead. Motivated by recent experiments demonstrating efficient manipulation of logical qubits using transversal gates [Bluvstein et al., Nature (London) 626, 58 (2024)NATUAS0028-083610.1038/s41586-023-06927-3], we show that the performance of logical algorithms can be substantially improved by decoding the qubits jointly to account for error propagation during transversal entangling gates. We find that such correlated decoding improves the performance of both Clifford and non-Clifford transversal entangling gates, and explore two decoders offering different computational runtimes and accuracies. In particular, by leveraging the deterministic propagation of stabilizer measurement errors, we find that correlated decoding enables the number of noisy syndrome extraction rounds between gates to be reduced from O(d) to O(1) in transversal Clifford circuits, where d is the code distance. We verify numerically that this approach substantially reduces the space-time cost of deep logical Clifford circuits. These results demonstrate that correlated decoding provides a major advantage in early fault-tolerant computation, as realized in recent experiments, and further indicate it has considerable potential to reduce the space-time cost in large-scale logical algorithms.

arXiv:2403.03272•Physical Review Letters•Dec 11, 2024•37 citations

Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC

Shota Ikari, Yuga Hirai, Yasunari Suzuki +2 more

Transversal CNOT (TCNOT) gates can accelerate fault-tolerant quantum computation (FTQC) in the surface code by reducing the number of syndrome extraction rounds required between logical operations from $O(d)$ to $O(1)$. This is particularly attractive for quantum platforms with long-range connectivity, such as neutral atoms. However, dense TCNOT schedules substantially increase the classical decoding workload. TCNOTs propagate errors across multiple surface-code patches, enlarging the spatiotemporal region that must be decoded jointly. Consequently, denser TCNOT schedules increase decoding latency and memory requirements and potentially exceed available decoder capacity. Moreover, because the detector error model (DEM) of each decoding window depends on the TCNOT schedule, exhaustively precomputing all possible window-level DEMs is infeasible, requiring just-in-time (JIT) DEM compilation. Thus, the practical benefit of TCNOT gates is limited not only by quantum hardware performance but also by classical decoding and DEM-compilation capacity. We introduce PACE, a decoder-aware scheduling framework for TCNOT-based FTQC. PACE first mitigates the decoder-side costs of aggressive TCNOT scheduling through three complementary techniques. Hybrid Window Decoding assigns different decoders for each decoding window according to its DEM structure. DEM Stitch generates schedule-specific window-level DEMs just in time by assembling reusable precompiled fragments. Sub-window Parallel Decoding decomposes large windows into smaller sub-windows with graph-coloring formulation. Building on these techniques, PACE then performs decoder-aware scheduling to maximize TCNOT concurrency within the available decoder resources. Our evaluation shows the trade-off between quantum acceleration and classical decoding cost, revealing the limitations of current decoding systems for TCNOT-based FTQC.

quant-pharXiv:2608.11719•Aug 13, 2026•0 citations

A Folded Surface Code Architecture for 2D Quantum Hardware

Zhu Sun, Zhenyu Cai

Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from $\mathcal{O}(d)$ in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal $S$ gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.

quant-pharXiv:2601.19823•Jan 28, 2026•0 citations

An Architecture for Improved Surface Code Connectivity in Neutral Atoms

Joshua Viszlai, Sophia Fuhui Lin, Siddharth Dangwal +2 more

In order to achieve error rates necessary for advantageous quantum algorithms, Quantum Error Correction (QEC) will need to be employed, improving logical qubit fidelity beyond what can be achieved physically. As today's devices begin to scale, co-designing architectures for QEC with the underlying hardware will be necessary to reduce the daunting overheads and accelerate the realization of practical quantum computing. In this work, we focus on logical computation in QEC. We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's higher physical connectivity into a higher logical connectivity. We propose groups of interleaved logical qubits, gaining all-to-all connectivity within the group via efficient transversal CNOT gates. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We also explore the architecture's scalability. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits. Using numerical simulations, we evaluate the total routing time of interleaved lattice surgery and atom movement for various circuit sizes. We identify a cross-over point defining intermediate-scale circuits where atom movement is best and large-scale circuits where interleaved lattice surgery is best. We use this to motivate a hybrid approach as devices continue to scale, with the choice of operation depending on the routing distance.

arXiv:2309.13507•Sep 24, 2023•4 citations

Parallel window decoding enables scalable fault tolerant quantum computation

Luka Skorić, Dan E. Browne, Kenton M. Barnes +2 more

Large-scale quantum computers have the potential to hold computational capabilities beyond conventional computers. However, the physical qubits are prone to noise which must be corrected in order to perform fault-tolerant quantum computations. Quantum Error Correction (QEC) provides the path for realizing such computations. QEC generates a continuous stream of data that decoders must process at the rate it is received, which can be as fast as 1 μs per QEC round in superconducting quantum computers. If the decoder infrastructure cannot keep up, a data backlog problem is encountered and the computation runs exponentially slower. Today's leading approaches to quantum error correction are not scalable as existing decoders typically run slower as the problem size is increased, inevitably hitting the backlog problem. Here, we show how to parallelize decoding to achieve almost arbitrary speed, removing this roadblock to scalability. Our parallelization requires some classical feed forward decisions to be delayed, slowing-down the logical clock speed. However, the slow-down is now only polynomial in the size of the QEC code, averting the exponential slowdown. We numerically demonstrate our parallel decoder for the surface code, showing no noticeable reduction in logical fidelity compared to previous decoders and demonstrating the predicted speedup.

arXiv:2209.08552•Nature Communications•Nov 3, 2023•81 citations
Atomic, molecular and optical (AMO) approaches to quantum computing are promising due to their increased connectivity, long coherence times and apparent scalability. However, they have a significantly reduced cadence of syndrome extraction compared to superconducting devices, a potentially crippling slow-down given the substantial logical gate counts required for quantum advantage. Transversal logic, which exploits higher connectivity, has the potential to significantly speed up the logical clock rate by reducing the number of syndrome extraction rounds required, but current decoders for fast transversal logic are not scalable. This is not just because existing decoders are too slow to handle the large decoding volumes resulting from fast logic; transversal logic breaks the key structural properties that make real-time decoding of lattice surgery efficient. We introduce two windowed decoding protocols for transversal logic in the surface code that restore modularity and locality to the decoding problem. Using our protocols, we show that, with a very small space overhead, our scalable decoders unlock an order of magnitude speedup for transversal logic compared to lattice surgery. Taken together, our results provide key evidence for the viability of large-scale algorithms on AMO qubits.
Quantum error correction (QEC) is required for large-scale computation, but incurs a significant resource overhead. Recent advances have shown that by jointly decoding logical qubits in algorithms composed of transversal gates, the number of syndrome extraction rounds can be reduced by a factor of the code distance ddd, at the cost of increased classical decoding complexity. Here, we reformulate the problem of decoding transversal circuits by directly decoding relevant logical operator products as they propagate through the circuit. This procedure transforms the decoding task into one closely resembling that of a single-qubit memory propagating through time. The resulting approach leads to fast decoding and reduced problem size while maintaining high performance. Focusing on the surface code, we prove that this method enables fault-tolerant decoding with minimum-weight perfect matching, and benchmark its performance on example circuits including magic state distillation. We find that the threshold is comparable to that of a single-qubit memory, and that the total decoding run time can be, in fact, less than that of conventional lattice surgery. Our approach enables fast correlated decoding, providing a pathway to directly extend single-qubit QEC techniques to transversal algorithms.
Quantum error correction is believed to be essential for scalable quantum computation, but its implementation is challenging due to its considerable space-time overhead. Motivated by recent experiments demonstrating efficient manipulation of logical qubits using transversal gates [Bluvstein et al., Nature (London) 626, 58 (2024)NATUAS0028-083610.1038/s41586-023-06927-3], we show that the performance of logical algorithms can be substantially improved by decoding the qubits jointly to account for error propagation during transversal entangling gates. We find that such correlated decoding improves the performance of both Clifford and non-Clifford transversal entangling gates, and explore two decoders offering different computational runtimes and accuracies. In particular, by leveraging the deterministic propagation of stabilizer measurement errors, we find that correlated decoding enables the number of noisy syndrome extraction rounds between gates to be reduced from O(d) to O(1) in transversal Clifford circuits, where d is the code distance. We verify numerically that this approach substantially reduces the space-time cost of deep logical Clifford circuits. These results demonstrate that correlated decoding provides a major advantage in early fault-tolerant computation, as realized in recent experiments, and further indicate it has considerable potential to reduce the space-time cost in large-scale logical algorithms.
Transversal CNOT (TCNOT) gates can accelerate fault-tolerant quantum computation (FTQC) in the surface code by reducing the number of syndrome extraction rounds required between logical operations from O(d)O(d)O(d) to O(1)O(1)O(1). This is particularly attractive for quantum platforms with long-range connectivity, such as neutral atoms. However, dense TCNOT schedules substantially increase the classical decoding workload. TCNOTs propagate errors across multiple surface-code patches, enlarging the spatiotemporal region that must be decoded jointly. Consequently, denser TCNOT schedules increase decoding latency and memory requirements and potentially exceed available decoder capacity. Moreover, because the detector error model (DEM) of each decoding window depends on the TCNOT schedule, exhaustively precomputing all possible window-level DEMs is infeasible, requiring just-in-time (JIT) DEM compilation. Thus, the practical benefit of TCNOT gates is limited not only by quantum hardware performance but also by classical decoding and DEM-compilation capacity. We introduce PACE, a decoder-aware scheduling framework for TCNOT-based FTQC. PACE first mitigates the decoder-side costs of aggressive TCNOT scheduling through three complementary techniques. Hybrid Window Decoding assigns different decoders for each decoding window according to its DEM structure. DEM Stitch generates schedule-specific window-level DEMs just in time by assembling reusable precompiled fragments. Sub-window Parallel Decoding decomposes large windows into smaller sub-windows with graph-coloring formulation. Building on these techniques, PACE then performs decoder-aware scheduling to maximize TCNOT concurrency within the available decoder resources. Our evaluation shows the trade-off between quantum acceleration and classical decoding cost, revealing the limitations of current decoding systems for TCNOT-based FTQC.
Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from O(d)\mathcal{O}(d)O(d) in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal SSS gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.
In order to achieve error rates necessary for advantageous quantum algorithms, Quantum Error Correction (QEC) will need to be employed, improving logical qubit fidelity beyond what can be achieved physically. As today's devices begin to scale, co-designing architectures for QEC with the underlying hardware will be necessary to reduce the daunting overheads and accelerate the realization of practical quantum computing. In this work, we focus on logical computation in QEC. We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's higher physical connectivity into a higher logical connectivity. We propose groups of interleaved logical qubits, gaining all-to-all connectivity within the group via efficient transversal CNOT gates. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We also explore the architecture's scalability. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits. Using numerical simulations, we evaluate the total routing time of interleaved lattice surgery and atom movement for various circuit sizes. We identify a cross-over point defining intermediate-scale circuits where atom movement is best and large-scale circuits where interleaved lattice surgery is best. We use this to motivate a hybrid approach as devices continue to scale, with the choice of operation depending on the routing distance.
Large-scale quantum computers have the potential to hold computational capabilities beyond conventional computers. However, the physical qubits are prone to noise which must be corrected in order to perform fault-tolerant quantum computations. Quantum Error Correction (QEC) provides the path for realizing such computations. QEC generates a continuous stream of data that decoders must process at the rate it is received, which can be as fast as 1 μs per QEC round in superconducting quantum computers. If the decoder infrastructure cannot keep up, a data backlog problem is encountered and the computation runs exponentially slower. Today's leading approaches to quantum error correction are not scalable as existing decoders typically run slower as the problem size is increased, inevitably hitting the backlog problem. Here, we show how to parallelize decoding to achieve almost arbitrary speed, removing this roadblock to scalability. Our parallelization requires some classical feed forward decisions to be delayed, slowing-down the logical clock speed. However, the slow-down is now only polynomial in the size of the QEC code, averting the exponential slowdown. We numerically demonstrate our parallel decoder for the surface code, showing no noticeable reduction in logical fidelity compared to previous decoders and demonstrating the predicted speedup.