CMOS-compatible processing and room-temperature characterization on wafer-level for scalable quantum computing
Simon Lang, Mayer, T., Johannes Weber, C. Dhieb, I. Eisele, W. Lerch, Zhenlin Luo, Carla Morán Guizán, Music, E., Leonhard Sturm-Rogon, Zahn, D., Rui N. Pereira, Christoph Kutter
We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 % and relaxation times (T1) approaching 80 us. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature (RT) characteristics collected from multiple wafers and fabrication runs, focusing on RT measurements and their correlation to low temperature qubit parameters. From defined test structures, an across-wafer Josephson junction (JJ) area variation of 10.1 % and oxide barrier variation of 7.2 % was calculated. Additionally, from the room-temperature JJ characterization the qubit frequency can be derived on wafer-level applying the Ambegaokar-Baratoff model before low temperature measurements. This sets the stage for pre-cooldown wafer-level JJ evaluation and sorting. In particular, such early-on device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, it enables the fabrication of large multichip quantum systems in the future. Our analysis highlight the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.
We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 % and relaxation times (T1) approaching 80 us. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature (RT) characteristics collected from multiple wafers and fabrication runs, focusing on RT measurements and their correlation to low temperature qubit parameters. From defined test structures, an across-wafer Josephson junction (JJ) area variation of 10.1 % and oxide barrier variation of 7.2 % was calculated. Additionally, from the room-temperature JJ characterization the qubit frequency can be derived on wafer-level applying the Ambegaokar-Baratoff model before low temperature measurements. This sets the stage for pre-cooldown wafer-level JJ evaluation and sorting. In particular, such early-on device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, it enables the fabrication of large multichip quantum systems in the future. Our analysis highlight the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.
We report on an industry-grade complementary metal-oxide semiconductor (CMOS)-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices that reaches 92.8%, with a resistance spread evaluated across the full wafer 200 mm in diameter of 12.4% and relaxation times T1 approaching $80\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}\mathrm{s}$. Furthermore, we conducted a comprehensive analysis of wafer-scale room-temperature (RT) characteristics collected from multiple wafers and fabrication runs, focusing on RT measurements and their correlation to low-temperature qubit parameters. From defined test structures, an across-wafer Josephson junction (JJ) area variation of 10.1% and oxide barrier variation of 7.2% was calculated. Additionally, from the room-temperature JJ characterization the qubit frequency can be derived at the wafer level by applying the Ambegaokar-Baratoff model before making low-temperature measurements. This sets the stage for precooldown wafer-level JJ evaluation and sorting. In particular, such early device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, this enables the fabrication of large multichip quantum systems in the future. Our analysis highlights the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.
We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.