The integration of photonic components into surface ion traps provides a scalable approach for trapped-ion quantum computing, sensing, and metrology, enabling compact systems with enhanced stability and precision. However, the introduction of optical apertures in the trap electrodes can distort the trapping electric field. This can lead to excess micromotion and ion displacement, which degrade the performance of quantum logic operations and optical clocks. In this work, we systematically investigate the electric field distortion in a surface ion trap with integrated waveguides and grating couplers that require apertures in the surface electrode using finite element method simulations. We analyze methods to reduce these distortions by exploiting symmetries and transparent conductive oxide materials.
The integration of photonic components into surface ion traps provides a scalable approach for trapped-ion quantum computing, sensing, and metrology, enabling compact systems with enhanced stability and precision. However, the introduction of optical apertures in the trap electrodes can distort the trapping electric field. This can lead to excess micromotion and ion displacement, which degrade the performance of quantum logic operations and optical clocks. In this work, we systematically investigate the electric field distortion in a surface ion trap with integrated waveguides and grating couplers that require apertures in the surface electrode using finite element method simulations. We analyze methods to reduce these distortions by exploiting symmetries and transparent conductive oxide materials.
Trapped-ion quantum computing requires precise optical control for individual qubit manipulation. However, conventional free-space optics face challenges in alignment stability and scalability as the number of qubits increases. Integrated photonics offers a promising alternative, providing miniaturized optical systems on a chip. Here, we propose a design for a multimode photonic circuit integrated with a surface-electrode ion trap capable of targeted and reconfigurable light delivery. Three closely positioned ions can be addressed using a focusing grating coupler that emits multimode light through electrode openings to ions trapped 80 μm above the chip. Simulations show that the couplers achieve diffraction-limited spot with a 4.3 μm beam waist along the trap axis and 2.2 μm perpendicular to the trap axis. Controlled interference of the TE10 and TE20 modes results in crosstalk of -20 dB to -30 dB at ion separations of 5-8 μm when addressing ions individually, and down to -60 dB when two of the three ions are addressed simultaneously. Additionally, the higher-order TE modes can offer a novel mechanism for driving spin-motion coupling transitions, potentially enabling alternative approaches to quantum gates and simulations. The proposed integrated platform offers a viable path for constructing large-scale trapped-ion systems, leveraging the benefits of nanophotonic design for precise and reliable ion manipulation.
Trapped-ion quantum computing requires precise optical control for individual qubit manipulation. However, conventional free-space optics face challenges in alignment stability and scalability as the number of qubits increases. Integrated photonics offers a promising alternative, providing miniaturized optical systems on a chip. Here, we propose a design for a multimode photonic circuit integrated with a surface-electrode ion trap capable of targeted and reconfigurable light delivery. Three closely positioned ions can be addressed using a focusing grating coupler that emits multimode light through electrode openings to ions trapped 68 μm above the chip. Simulations show that the couplers achieve a diffraction-limited spot with a 4.3 μm beam waist along the trap axis and 2.2 μm perpendicular to the trap axis. Controlled interference of the TE 00 and TE 10 modes results in crosstalk of –20 dB to –30 dB at ion separations of 5–8 μm when addressing ions individually, and down to –60 dB when two of the three ions are addressed simultaneously. Additionally, the higher-order TE modes can offer a novel mechanism for driving spin-motion coupling transitions, potentially enabling alternative approaches to quantum gates and simulations. The proposed integrated platform offers a viable path for constructing large-scale trapped-ion systems, leveraging the benefits of nanophotonic design for precise and reliable ion manipulation.
Trapped-ion qubits have been advantageous in quantum information processing due to their long coherence times and high-fidelity state preparation, logic gate operation, and readout. In recent years, we have fabricated chips with electrodes – for generating the electric field for trapping ions – and photonic waveguides and grating out-couplers – for delivering light to the ions. The integrated photonics can potentially lower the laser power requirement and lead to faster gates; however, there are challenges that need to be overcome for the platform to be beneficial. Here, we demonstrate single and two qubit gates with Sr+ trapped ion qubits, driven by delivering light to the ions both via free space and integrated photonics. We show that robust quantum logic is within reach using the integrated photonic platform, and the approaches we are taking in mitigating current challenges.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
We study a range of radio-frequency ion trap geometries and investigate the effect of integrating dielectric cavity mirrors on their trapping potential using numerical modelling. We compare five different ion trap geometries with the aim to identify ion trap and cavity configurations that are best suited for achieving small cavity volumes and thus large ion-photon coupling as required for scalable quantum information networks. In particular, we investigate the trapping potential distortions caused by the dielectric material of the cavity mirrors in all 3 dimensions for different mirror orientations with respect to the trapping electrodes. We also analyze the effect of the mirror material properties such as dielectric constants and surface conductivity, and study the effect of surface charges on the mirrors. As well as perfectly symmetric systems, we also consider traps with optical cavities that are not centrally aligned where we find a spatial displacement of the trap centre and asymmetry of the resulting trap only at certain cavity orientations. The best trapcavity configurations with the smallest trapping potential distortions are those where the cavities are aligned along the major symmetry axis of the electrode geometries. These cavity configurations also appear to be the most stable with respect to any mirror misalignment. Although we consider particular trap sizes in our study, the presented results can be easily generalized and scaled to different trap dimensions.
The integration of optics for efficient light delivery and the collection of fluorescence from trapped ions in surface electrode ion traps is a key component to achieving scalability for quantum information processing. Diffractive optical elements (DOEs) present a promising approach as compared to bulk optics because of their small physical profile and their flexibility in tailoring the optical wavefront. The precise alignment of the optics for coupling fluorescence to and from the ions, however, poses a particular challenge. Excitation and manipulation of the ions requires a high degree of optical access, significantly restricting the area available for mounting components. The ion traps, DOEs, and other components are compact, constraining the manipulation of various elements. For efficient fluorescence collection from the ions the DOE must be have a large numerical aperture (NA), which results in greater sensitivity to misalignment. The ion traps are sensitive devices, a mechanical approach to alignment such as contacting the trap and using precision motors to back-off a set distance not only cannot achieve the desired alignment precision, but risks damage to the ion trap. We have developed a non-contact precision optical alignment technique. We use line foci produced by off-axis linear Fresnel zone plates (FZPs) projected on alignment targets etched in the top metal layer of the ion trap and demonstrate micron-level alignment accuracy.