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arXiv:2503.14951 · International Conference on Integrated Circuits, Design, and Verification (ICDV)

QEA: An Accelerator for Quantum Circuit Simulation with Resources Efficiency and Flexibility

Van Duy Tran, Vu Tuan Hai, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima

Published Jun 16, 2025• 4 citations
arXivHTMLPDF

Abstract

The area of quantum circuit simulation has attracted a lot of attention in recent years. However, due to the exponentially increasing computational costs, assessing and validating these models on large datasets poses significant obstacles. Despite plenty of research in quantum simulation, issues such as memory management, system adaptability, and execution efficiency remain unresolved. In this study, we introduce QEA, a state vector-based hardware accelerator that overcomes these difficulties with four key improvements: optimized memory allocation management, open PE, flexible ALU, and simplified CX swapper. To evaluate QEA's capabilities, we implemented and evaluated it on the AMD Alveo U280 board, which uses only 0.534 W of power. Experimental results show that QEA is extremely flexible, supporting a wide range of quantum circuits, has excellent fidelity, making it appropriate for standard quantum emulators, and outperforms powerful CPUs and related works up to$153.16 \times$better in terms of normalized gate speed. This study has considerable potential as a useful approach for quantum emulators in future works.

DOI
10.1109/icdv66179.2025.11135229

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The area of quantum circuit simulation has attracted a lot of attention in recent years. However, due to the exponentially increasing computational costs, assessing and validating these models on large datasets poses significant obstacles. Despite plenty of research in quantum simulation, issues such as memory management, system adaptability, and execution efficiency remain unresolved. In this study, we introduce QEA, a state vector-based hardware accelerator that overcomes these difficulties with four key improvements: optimized memory allocation management, open PE, flexible ALU, and simplified CX swapper. To evaluate QEA's capabilities, we implemented and evaluated it on the AMD Alveo U280 board, which uses only 0.534 W of power. Experimental results show that QEA is extremely flexible, supporting a wide range of quantum circuits, has excellent fidelity, making it appropriate for standard quantum emulators, and outperforms powerful CPUs and related works up to153.16×153.16 \times153.16×better in terms of normalized gate speed. This study has considerable potential as a useful approach for quantum emulators in future works.
In recent years, there has been a growing interest in the development of quantum emulation. However, existing studies often struggle to achieve broad applicability, high performance, and efficient resource and memory utilization. To address these challenges, we provide HPQEA, a quantum emulator based on the state-vector emulation approach. HPQEA includes three main features: a high-performance computing core, an optimized controlled-NOT gate computation strategy, and effective utilization of high-bandwidth memory. Verification and evaluation on the Alveo U280 board show that HPQEA can emulate quantum circuits with up to 30 qubits while maintaining high fidelity and low mean square error. It outperforms comparable FPGA-based systems by producing faster execution, supporting a wider range of algorithms, and requiring low hardware resources. Furthermore, it exceeds the Nvidia A100 in normalized gate speed for systems with up to 20 qubits. These results demonstrate the scalability and efficiency of HPQEA as a platform for emulating quantum algorithms.
ABSTRACT In recent years, quantum emulation has attracted increasing attention as a practical approach for developing and evaluating quantum algorithms. However, existing solutions often face challenges in achieving broad applicability, high performance, and efficient utilization of hardware resources and memory. To address these limitations, this paper presents the high‐performance quantum emulation accelerator (HPQEA), a hardware architecture based on the state‐vector emulation approach. The proposed design incorporates four key techniques: a strict data storage strategy, a superior flexible processing element network, an optimized and parallelized CX swapper, and a high‐bandwidth memory‐based bulk data transfer engine. Implementation and evaluation on the Alveo U280 FPGA platform demonstrate that HPQEA can emulate quantum circuits efficiently while maintaining high fidelity and low mean square error. Experimental results show that for QFT benchmarks, HPQEA achieves up to 21,093 faster execution than the NVIDIA A100 GPU for circuits with fewer than 20 qubits. Moreover, the comparison with FPGA‐based related works shows promising results with significant speedup in terms of normalize gate speed from 2.77 to 1448.37. In addition, the architecture demonstrates strong energy efficiency, reducing power consumption by up to 15.58 compared to the Intel i9‐10940X CPU and 80.83 compared to the GTX 1080 GPU. These results highlight the scalability, efficiency, and practicality of HPQEA as a hardware platform for accelerating quantum algorithm emulation.
Classical simulation of quantum circuits remains indispensable for algorithm development, hardware validation, and error analysis in the noisy intermediate-scale quantum (NISQ) era. However, state-vector simulation faces exponential memory scaling, with an n-qubit system requiring O(2^n) complex amplitudes, and existing simulators often lack the flexibility to exploit heterogeneous computing resources at runtime. This paper presents a GPU-accelerated quantum circuit simulation framework that introduces three contributions: (1) an empirical backend selection algorithm that benchmarks CuPy, PyTorch-CUDA, and NumPy-CPU backends at runtime and selects the optimal execution path based on measured throughput; (2) a directed acyclic graph (DAG) based gate fusion engine that reduces circuit depth through automated identification of fusible gate sequences, coupled with adaptive precision switching between complex64 and complex128 representations; and (3) a memory-aware fallback mechanism that monitors GPU memory consumption and gracefully degrades to CPU execution when resources are exhausted. The framework integrates with Qiskit, Cirq, PennyLane, and Amazon Braket through a unified adapter layer. Benchmarks on an NVIDIA A100-SXM4 (40 GiB) GPU demonstrate speedups of 64x to 146x over NumPy CPU execution for state-vector simulation of circuits with 20 to 28 qubits, with speedups exceeding 5x from 16 qubits onward. Hardware validation on an IBM quantum processing unit (QPU) confirms Bell state fidelity of 0.939, a five-qubit Greenberger-Horne-Zeilinger (GHZ) state fidelity of 0.853, and circuit depth reduction from 42 to 14 gates through the fusion pipeline. The system is designed for portability across NVIDIA consumer and data-center GPUs, requiring no vendor-specific compilation steps.
Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to current quantum device limitations. Software simulators are time and memory-intensive, making hardware emulators an attractive alternative. This article introduces a digital architecture, designed to emulate quantum computing on low-tier Field-Programmable Gate Arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates quantum algorithm verification using a RISC-like structure and efficiently handling sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. The architecture is validated against the Qiskit state vector simulator, successfully emulating sixteen qubits on a Xilinx Kria KV260 SoM.
The classical simulation of quantum algorithms is a crucial tool for circuit development, testing, and validation. Although acceleration using GPUs significantly reduces simulation time, most high-performance simulators rely on vendor-specific frameworks that target data-center hardware. To broaden access to quantum simulation, this work proposes a vendor-agnostic approach targeting the integrated GPUs commonly found in consumer-grade laptops. A primary challenge in state-vector simulation is its inherently poor spatial locality, which creates a memory bandwidth bottleneck. Consequently, baseline implementations experience a severe degradation in relative GPU speedup as the number of simulated qubits increases. To address this limitation, we introduce a state partitioning optimization that reorganizes the quantum state vector to maximize the last-level cache locality and minimize costly main memory fetches. We evaluate this strategy using a Quantum Phase Estimation algorithm across diverse architectures from Intel, AMD, and Apple. The experimental results demonstrate that the proposed optimization successfully mitigates performance degradation at larger qubit scales. In particular, for a 28-qubit simulation, the optimization reversed a performance deficit on an Intel Core i5, improving the GPU speedup over the CPU from 0.95x to 1.89x, and increased the Apple M1 Pro speedup from 3.71x to 5.88x. Overall, this approach yields consistent execution time improvements, demonstrating the viability of integrated GPUs for efficient quantum circuit simulation.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with nnn qubits requires 2n+42^{n+4}2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.