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arXiv:2503.03544 · ACM/IEEE Design Automation Conference (DAC)

KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA

Xiaorang Guo, Tigran Bunarjyan, Dai Liu, Benjamin Lienhard, Martin Schulz

Published Jun 22, 2025• 1 citation
arXivHTMLPDF

Abstract

Superconducting qubits are among the most promising candidates for building quantum information processors. Yet, they are often limited by slow and error-prone qubit readout-a critical factor in achieving high-fidelity operations. While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely on large, resource-intensive network models. This paper presents KLiNQ, a novel qubit readout architecture leveraging lightweight neural networks optimized via knowledge distillation. Our approach achieves around a $99 \%$ reduction in model size compared to the baseline while maintaining a qubitstate discrimination accuracy of $91 \%$. KLiNQ facilitates rapid, independent qubit-state readouts that enable mid-circuit measurements by assigning a dedicated, compact neural network for each qubit. Implemented on the Xilinx UltraScale+ FPGA, our design can perform the discrimination within 32 ns. The results demonstrate that compressed neural networks can maintain highfidelity independent readout while enabling efficient hardware implementation, advancing practical quantum computing.

DOI
10.1109/dac63849.2025.11132854

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Superconducting qubits are among the most promising candidates for building quantum information processors. Yet, they are often limited by slow and error-prone qubit readout-a critical factor in achieving high-fidelity operations. While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely on large, resource-intensive network models. This paper presents KLiNQ, a novel qubit readout architecture leveraging lightweight neural networks optimized via knowledge distillation. Our approach achieves around a 99%99 \%99% reduction in model size compared to the baseline while maintaining a qubitstate discrimination accuracy of 91%91 \%91%. KLiNQ facilitates rapid, independent qubit-state readouts that enable mid-circuit measurements by assigning a dedicated, compact neural network for each qubit. Implemented on the Xilinx UltraScale+ FPGA, our design can perform the discrimination within 32 ns. The results demonstrate that compressed neural networks can maintain highfidelity independent readout while enabling efficient hardware implementation, advancing practical quantum computing.
Machine learning has emerged as a promising approach for the accurate state discrimination of multiplexed superconducting qubits. However, existing methods often rely on large, resource-intensive models, posing challenges for efficient hardware deployment. In this work, we present a lightweight neural network optimized via knowledge distillation, achieving a 99% reduction in model size while maintaining comparable readout fidelity. Furthermore, we implement the proposed approach on a Xilinx FPGA, achieving a readout latency of only 32 ns
This work presents QubiCML, a novel FPGA-based system engineered for real-time, in-situ discrimination of two- and three-level quantum states (quitrits) in superconducting quantum processors. Accurate and low-latency identification of quantum states is a critical enabler for scaling quantum computing, particularly as higher-dimensional systems such as qutrits are explored to increase information density, circuit depth, and gate expressivity. QubiCML integrates a lightweight, multi-layer neural network directly into FPGA hardware to classify the qutrit states∣g⟩,∣e⟩\vert g\rangle,\vert e\rangle∣g⟩,∣e⟩, and∣f⟩\vert f\rangle∣f⟩with high fidelity and minimal latency. Traditional state discrimination methods rely on offline post-processing, resulting in delays incompatible with the short coherence times of superconducting qubits. QubiCML overcomes this bottleneck by performing all inference operations within the FPGA fabric itself, achieving full quantum state discrimination within 66 ns (with softmax) or 40 ns (without softmax). The system supports fast reconfiguration via BRAM-stored parameters, enabling compatibility with varying quantum hardware and dynamic calibration environments. Additionally, we propose FPGA-friendly techniques for data normalization and fixed-point quantization to eliminate the overhead of floating-point and division operations—further optimizing the architecture for real-time deployment. We evaluate QubiCML on in-house superconducting hardware across multiple qubits and qutrits. The system achieves up to 97 % average accuracy for qutrits and up to 99 % for two-level systems, using readout windows as short as 650-750 ns. These results establish QubiCML as one of the first practical implementations of real-time qutrit state discrimination, marking an essential step toward mid-circuit measurements, dynamic feedback, and advanced error correction in higher-dimensional quantum computing.
Identifying the state of a quantum bit (qubit), known as quantum state discrimination, is a crucial operation in quantum computing. However, it has been the most error-prone and time-consuming operation on superconducting quantum processors. Due to stringent timing constraints and algorithmic complexity, most qubit state discrimination methods are executed offline. In this work, we present an enhanced real-time quantum state discrimination system leveraging FPGA-based AI Engine technology. A multi-layer neural network has been developed and implemented on the AMD Xilinx VCK190 FPGA platform, enabling accurate in-situ state discrimination and supporting mid-circuit measurement experiments for multiple qubits. Our approach leverages recent advancements in architecture research and design, utilizing specialized AI/ML accelerators to optimize quantum experiments and reduce the use of FPGA resources.
Measuring a qubit state is a fundamental but error-prone task in quantum computing. As the number of qubits increases, scalable readout demands multiplexed qubit measurement, which often suffers from crosstalk and other nonidealities. The conventional approach of qubit state detection often struggles with scalability and noise resilience. Neural network (NN)-based discriminators have emerged as a promising alternative, offering superior performance for inferring qubit states from multiplexed signals. However, their deployment on hardware platforms like Field programmable gate arrays (FPGA) is hindered by computation complexity, resource constraints, and latency. In this work, we present an end-to-end methodology for designing and deploying quantized NN-based multi-qubit state discriminators on FPGAs. We demonstrate that implementing a fully connected neural network accelerator for multi-qubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. We significantly reduce the FPGA footprint and latency of the neural network by employing quantization-aware training (QAT) to quantize weights, activations, and inputs, and leveraging automated mapping flows for efficient, hardware-aware design-space exploration and optimization. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in 26.7 ns, on a radio frequency system on chip (RFSoC) ZCU111 FPGA. These modules can be implemented and integrated into existing FPGA based quantum control and readout platforms, making them ready for experimental deployment.
Quantum Neural Networks (QNNs) are a promising class of quantum machine learning models with potential quantum advantages when implemented on scalable, error-corrected quantum computers. However, as system sizes increase, deploying QNNs becomes challenging. Similar to their classical counterparts, a key obstacle to their practical applications is that large-scale QNNs may not be easily deployed on smaller systems that have limited resources. Here, we tackle this challenge by compressing QNNs via knowledge distillation. We demonstrate how well-trained QNNs on large systems can be distilled into smaller architectures with similar configurations. We numerically show that knowledge distillation helps reduce the training cost of QNNs in terms of the number of qubits and circuit depth. Additionally, we find that a self-knowledge-distillation approach can accelerate training convergence. We believe our results offer new strategies for the efficient compression and practical deployment of QNNs.
Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by 60×60 \times60× compared to the baseline while reducing readout time by 20%20 \%20%, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a 100×100 \times100× reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a 6.6%6.6 \%6.6% relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward faulttolerant quantum computing.