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arXiv:2502.19872 · Quantum Science and Technology

Designing a machine learning-driven, cross-hardware emulator for noisy quantum computers with gate-based protocols

Matthew Ho, Jun Yong Khoo, Adrian Matthew Mak, Stefano Carrazza

Published May 7, 2026• 0 citations
arXivHTMLPDF

Abstract

Abstract Quantum computer emulators model the behavior and error rates of specific quantum processors. Without accurate noise models in these emulators, it is challenging for users to optimize and debug executable quantum programs prior to running them on the quantum computer, as device-specific noise is not properly accounted for. To overcome this challenge, we design a machine learning (ML)-driven approach to construct approximate device-specific emulators that applies to different hardware platforms. We apply supervised ML on a pre-generated library containing simulated gate set tomography training data. The ML model then analyses gate set tomography data from a target quantum computer to predict its noise model, which is in turn used to construct the device-specific emulator. We demonstrate the effectiveness of our protocol’s emulator in estimating the unitary coupled cluster energy of the H 2 molecule and compare the results with those from actual quantum hardware. Remarkably, our noise model captures device noise with high accuracy, achieving a percentage relative error of just 0.128% in expectation value relative to the actual quantum hardware. Importantly, we show that even without access to pulse-level control, noise from the quantum computer can nonetheless be characterized and independently validated by our protocol.

DOI
10.1088/2058-9565/ae6a1c

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Abstract Quantum computer emulators model the behavior and error rates of specific quantum processors. Without accurate noise models in these emulators, it is challenging for users to optimize and debug executable quantum programs prior to running them on the quantum computer, as device-specific noise is not properly accounted for. To overcome this challenge, we design a machine learning (ML)-driven approach to construct approximate device-specific emulators that applies to different hardware platforms. We apply supervised ML on a pre-generated library containing simulated gate set tomography training data. The ML model then analyses gate set tomography data from a target quantum computer to predict its noise model, which is in turn used to construct the device-specific emulator. We demonstrate the effectiveness of our protocol’s emulator in estimating the unitary coupled cluster energy of the H 2 molecule and compare the results with those from actual quantum hardware. Remarkably, our noise model captures device noise with high accuracy, achieving a percentage relative error of just 0.128% in expectation value relative to the actual quantum hardware. Importantly, we show that even without access to pulse-level control, noise from the quantum computer can nonetheless be characterized and independently validated by our protocol.
Maximizing the computational utility of near-term quantum processors requires predictive noise models that inform robust, noise-aware compilation and error mitigation. Conventional models often fail to capture the complex error dynamics of real hardware or require prohibitive characterization overhead. We introduce a data-efficient framework that first constructs a physically motivated, parameterized noise model, and subsequently employs machine-learning-driven Bayesian optimization to identify its parameters. Our approach circumvents costly characterization protocols by estimating algorithm- and hardware-specific error parameters directly from readily available experimental data derived from existing application and benchmark circuit executions. The generality and robustness of the framework are demonstrated across diverse algorithms and superconducting devices, yielding high-fidelity predictions by estimating an independent parameter set tailored to each specific algorithm-hardware context. Crucially, we show that a model calibrated exclusively on small-scale circuits accurately predicts the behavior of larger validation circuits. Our data-efficient approach achieves up to a 65% improvement in model fidelity quantified by the Hellinger distance between predicted and experimental circuit output distributions, compared to standard noise models derived from device properties. This work establishes a practical paradigm for application-aware noise characterization, enabling compilation and error-mitigation strategies tailored to the specific interplay between quantum algorithms and device-specific noise dynamics.
Analog quantum processors based on Rydberg atom arrays are a powerful platform for many-body quantum simulation, combinatorial optimization, and graph machine learning. As these devices become increasingly accessible, establishing confidence in their outputs requires predictive models that quantitatively connect microscopic hardware imperfections to empirical results. Here, we present a noise-aware emulation framework that propagates the dominant noise mechanisms throughout the full computation cycle to predict device behavior. We validate the framework by benchmarking two representative protocols, quantum annealing and post-quench dynamics, on three Pasqal quantum processors where classical simulations still provide ground truth. Across all three devices, the measured observables fall within the uncertainty envelopes predicted by the emulator. Beyond reproducing the data, the framework isolates which physical mechanism dominates in each operating regime, provides quantitative guidance for algorithm design and hardware improvements, and establishes a foundation for verifying analog processors in regimes beyond classical reach.
Quantum characterization, validation, and verification (QCVV) techniques are used to probe, characterize, diagnose, and detect errors in quantum information processors (QIPs). An important component of any QCVV protocol is a mapping from experimental data to an estimate of a property of a QIP. Machine learning (ML) algorithms can help automate the development of QCVV protocols, creating such maps by learning them from training data. We identify the critical components of "machine-learned" QCVV techniques, and present a rubric for developing them. To demonstrate this approach, we focus on the problem of determining whether noise affecting a single qubit is coherent or stochastic (incoherent) using the data sets originally proposed for gate set tomography. We leverage known ML algorithms to train a classifier distinguishing these two kinds of noise. The accuracy of the classifier depends on how well it can approximate the "natural" geometry of the training data. We find GST data sets generated by a noisy qubit can reliably be separated by linear surfaces, although feature engineering can be necessary. We also show the classifier learned by a support vector machine (SVM) is robust under finite-sample noise.
Despite significant efforts, the realization of the hybrid quantum-classical algorithms has predominantly been confined to proof-of-principles, mainly due to the hardware noise. With fault-tolerant implementation being a long-term goal, going beyond small molecules with existing error mitigation (EM) techniques with current noisy intermediate scale quantum (NISQ) devices has been a challenge. That being said, statistical learning methods are promising approaches to learning the noise and its subsequent mitigation. We devise a graph neural network and regression-based machine learning (ML) architecture for practical realization of EM techniques for molecular Hamiltonian without the requirement of the exponential overhead. Given the short coherence time of the quantum hardware, the ML model is trained with either ideal or mitigated expectation values over a judiciously chosen ensemble of shallow sub-circuits adhering to the native hardware architecture. The hardware connectivity network is mapped to a directed graph which encodes the information of the native gate noise profile to generate the features for the neural network. The training data is generated on-the-fly during ansatz construction thus removing the computational overhead. We demonstrate orders of magnitude improvements in predicted energy over a few strongly correlated molecules.
We present an approach for a deep-learning compiler of quantum circuits, designed to reduce the output noise of circuits run on a specific device. We train a convolutional neural network on experimental data from a quantum device to learn a hardware-specific noise model. A compiler then uses the trained network as a noise predictor and inserts sequences of gates in circuits so as to minimize expected noise. We tested this approach on the IBM 5-qubit devices and observed a reduction in output noise of 12.3% (95% CI [11.5%, 13.0%]) compared to the circuits obtained by the Qiskit compiler. Moreover, the trained noise model is hardware-specific: applying a noise model trained on one device to another device yields a noise reduction of only 5.2% (95% CI [4.9%, 5.6%]). These results suggest that device-specific compilers using machine learning may yield higher fidelity operations and provide insights for the design of noise models.
Hybridizing machine learning (ML) with quantum computing has become an attractive strategy to increase computational power on Noisy Intermediate Scale Quantum (NISQ) devices. Although these can be potentially quantum advantage devices, their qubit numbers and noise are bounded and there are challenges when it comes to practical quantum circuit realization. This work concentrates on the creation of optimized quantum circuits via ML-based strategies, to enhance the performance of the circuits, to reduce the error rate and to accommodate the particular noise profile of the hardware of NISQ devices. The resulting suboptimal mappings with little or no consideration of noise and hardware topology in traditional quantum compilers can ruin the fidelity of quantum algorithm. Leveraging machine learning, and specifically reinforcement and supervised learning methods, our method learns to optimize compilation strategy for specific quantum hardware architecture. The paper proposes a framework that uses machine learning models to predict qubit mappings, gate decompositions, and transpilation paths that minimize gate depth and error accumulation. We also investigate transfer learning methods for propagating the learned compilation strategies to novel NISQ machines. Such methods are empirically validated on both simulated and real quantum hardware backends, providing evidence of circuit depth, execution time and error reductions. The results show that ML-assisted compilation can achieve better success probabilities for benchmark quantum algorithms like VQE and QAOA than conventional compilers. Furthermore, the work examines the interpretability of ML models providing hardware-aware optimization recommendations and understanding the noise patterns and methods of error correction. Our work highlights the key role of ML for transferring between theoretical quantum algorithms and their practical NISQ implementations. This integration boosts the immediate applicability of existing quantum devices and provides a basis for adaptive and scalable likelihood-based compilation for the era of fault-tolerant quantum computation. Our results motivate further investigation of hybrid classical-quantum workflows, in which ML iteratively improves compilation in accordance with changing hardware noise and capabilities. By improving quantum circuit compilation onNISQ computers, this work is taking steps toward the realization of quantum advantage in application scenarios such as optimization, cryptography, and quantum simulation without needing to wait for fully fault-tolerant large-scale quantum computers.