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arXiv:2501.14102

5G LDPC Linear Transformer for Channel Decoding

Hernandez, Mario, Fernando Piñero

Published Jan 23, 2025• 0 citations
arXivHTMLPDF

Abstract

This work introduces a novel, fully differentiable linear-time complexity transformer decoder and a transformer decoder to correct 5G New Radio (NR) LDPC. We propose a scalable approach to decode linear block codes with $O(n)$ complexity rather than $O(n^2)$ for regular transformers. The architectures' performances are compared to Belief Propagation (BP), the production-level decoding algorithm used for 5G New Radio (NR) LDPC codes. We achieve bit error rate performance that matches a regular Transformer decoder and surpases one iteration BP, also achieving competitive time performance against BP, even for larger block codes. We utilize Sionna, Nvidia's 5G & 6G physical layer research software, for reproducible results.

DOI
10.48550/arxiv.2501.14102

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This work introduces a novel, fully differentiable linear-time complexity transformer decoder and a transformer decoder to correct 5G New Radio (NR) LDPC. We propose a scalable approach to decode linear block codes with O(n)O(n)O(n) complexity rather than O(n2)O(n^2)O(n2) for regular transformers. The architectures' performances are compared to Belief Propagation (BP), the production-level decoding algorithm used for 5G New Radio (NR) LDPC codes. We achieve bit error rate performance that matches a regular Transformer decoder and surpases one iteration BP, also achieving competitive time performance against BP, even for larger block codes. We utilize Sionna, Nvidia's 5G & 6G physical layer research software, for reproducible results.
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In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.
Abstract In order to cater to the needs of the 5G standard, one of the prominent solutions in terms of high coding gain, high throughput and low power dissipation is the 5G NR LDPC (New Radio Low Density Parity Check) codes which have been adopted by 5G Standard. LDPC codes are the successful Third Generation Forward Error Correcting codes. An Efficient decoder is the key to the success of any Error Correcting Code. LDPC codes are one whose parity check matrix have a very few non zero entries. 5G NR LDPC codes are constructed by Protographs or base graphs and are block structured. This paper improves the performance of Layered Iterative minsum Approximation Message Passing decoding Algorithm using Rate Matching, Fixed Point Quantization and Offset minsum techniques. Rate Matching is to maintain the exact number of encoded blocks with in the TTI. Simulation of this algorithm with BPSK encoding over AWGN channel shows that BER of 10-3 gives Eb/No of~2 dB for the block length of 105.
This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.
Low-density parity-check (LDPC) codes have been chosen for the fifth-generation (5G) new radio (NR) enhanced Mobile Broad Band (eMBB) data channel. Since NR LDPC codes puncture the first two block columns of the parity-check matrix, the decoding complexity is reduced, but it slows down the convergence rate. In this letter, we propose a fixed schedule that decodes the layers with the least-punctured edges and those with the highest-degree (LPHD), which has much faster convergence speed than conventional schemes. The fixed scheduling schemes cannot take full advantage of the dynamic changes of decoding messages. As a result, the residual-based layered belief propagation (RB-LBP) is proposed to rearrange the layers dynamically among different iterations. Compared with some informed dynamic scheduling (IDS) strategies, RB-LBP reduces the decoding complexity with slight performance loss.