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arXiv:2501.10291

Low-overhead Magic State Circuits with Transversal CNOTs

Fazio, Nicholas, Webster, Mark, Zhenyu Cai

Published Jan 17, 2025• 0 citations
arXivHTMLPDF

Abstract

With the successful demonstration of transversal CNOTs in many recent experiments, it is the right moment to examine its implications on one of the most critical parts of fault-tolerant computation -- magic state preparation. Using an algorithm that can recompile and simplify a circuit of consecutive multi-qubit phase rotations, we manage to construct fault-tolerant circuits for CCZ, CS and T states with much lower CNOT depths and qubit counts than before and minimal T-depth for the given workspace. These circuits can play crucial roles in fault-tolerant computation with transversal CNOTs, and we hope that the algorithms and methods developed in this paper can be used to further simplify other protocols in similar contexts.

DOI
10.48550/arxiv.2501.10291

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With the successful demonstration of transversal CNOTs in many recent experiments, it is the right moment to examine its implications on one of the most critical parts of fault-tolerant computation -- magic state preparation. Using an algorithm that can recompile and simplify a circuit of consecutive multi-qubit phase rotations, we manage to construct fault-tolerant circuits for CCZ, CS and T states with much lower CNOT depths and qubit counts than before and minimal T-depth for the given workspace. These circuits can play crucial roles in fault-tolerant computation with transversal CNOTs, and we hope that the algorithms and methods developed in this paper can be used to further simplify other protocols in similar contexts.
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The full potential of quantum computers will be attainable when large devices can employ quantum error correction and attain fault-tolerance. Great strides have been made, with experimental demonstrations of pivotal components for quantum error correction on a variety of platforms, substantiating that the foundations for fault-tolerant logic are realisable. This thesis explores the kinds of noise we expect to find at the logical level while employing schemes for fault-tolerance in this emerging period and how we may optimise such schemes. We study how a noise characteristic called bias is transformed in the implementation of a fault-tolerant gadget for the T-gate. We show that noise bias is amplified at the logical level due to error correction, which is furthermore affected by the noise-transforming properties of the injection gadget, which separately induces logical phase bias. We experimentally characterise the noise on a trapped-ion quantum computer. We target a logical CNOT with this method such that we are able to: understand and mitigate control layer imperfections, account for the distinction in noise characteristics between individual CNOT and transversal CNOTs, and make predictions on logical level performance if these transversal CNOTs are used as a logical CNOT for the Steane code. This is achieved by leveraging information about correlated noise across the device from the physical characterisation of gates, demonstrating that such diagnostic information can be learned scalably. Finally, noting the transversal gate capabilities of recent architectures, we optimise fault-tolerant circuits for preparing magic states in that setting. We describe an algorithm that recompiles and synthesises such circuits for minimal T-depth and low CNOT depth, while maintaining the total qubit count. We apply this algorithm to fault-tolerant circuits for |CCZ>, |CS> and |T> and show how we can reduce overheads for preparing magic states.
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