Circuit cutting is a promising technique that leverages both quantum and classical computational resources, enabling the practical execution of large quantum circuits on noisy intermediate-scale quantum (NISQ) hardware. Recent approaches typically focus exclusively on either gate cuts or wire cuts, modeling quantum circuits as graphs. However, identifying optimal cutting locations using this representation often results in prohibitively high computational complexity, especially under realistic hardware constraints. In this paper, we introduce CiFold, a novel graph-based framework that exploits repetitive modular structures inherent in quantum algorithms, significantly enhancing the scalability and efficiency of circuit cutting. Our approach systematically folds quantum circuits into compact meta-graphs by identifying and merging common gate sequences across entangled qubits, dramatically simplifying subsequent partitioning tasks. We define folding factor and variance to quantify circuit compression and ensure balanced folding. Using these condensed representations, CiFold precisely identifies cut locations without exhaustive global graph searches. We perform extensive experiments, comparing CiFold with state-of-the-art circuit-cutting techniques. Results demonstrate that CiFold achieves superior partition quality and computational efficiency, reducing the number of required cuts by an average of 31.6% and lowering the sampling overhead substantially by 3.55 × 109. Our findings illustrate that CiFold represents a significant advancement toward scalable quantum circuit cutting.
Circuit cutting is a promising technique that leverages both quantum and classical computational resources, enabling the practical execution of large quantum circuits on noisy intermediate-scale quantum (NISQ) hardware. Recent approaches typically focus exclusively on either gate cuts or wire cuts, modeling quantum circuits as graphs. However, identifying optimal cutting locations using this representation often results in prohibitively high computational complexity, especially under realistic hardware constraints. In this paper, we introduce CiFold, a novel graph-based framework that exploits repetitive modular structures inherent in quantum algorithms, significantly enhancing the scalability and efficiency of circuit cutting. Our approach systematically folds quantum circuits into compact meta-graphs by identifying and merging common gate sequences across entangled qubits, dramatically simplifying subsequent partitioning tasks. We define folding factor and variance to quantify circuit compression and ensure balanced folding. Using these condensed representations, CiFold precisely identifies cut locations without exhaustive global graph searches. We perform extensive experiments, comparing CiFold with state-of-the-art circuit-cutting techniques. Results demonstrate that CiFold achieves superior partition quality and computational efficiency, reducing the number of required cuts by an average of 31.6% and lowering the sampling overhead substantially by 3.55 × 109. Our findings illustrate that CiFold represents a significant advancement toward scalable quantum circuit cutting.
Quantum circuit cutting enables the execution of large circuits on devices with a limited number of qubits by partitioning circuits into independent subcircuits. However, this introduces a sampling overhead, which grows exponentially with the number of cuts, rendering the choice of cut placements critical for practical circuit cutting. Determining optimal cut placements remains computationally challenging, particularly as circuits grow in size. Additionally, existing circuit cutting approaches typically treat gate and wire cuts independently. Those combining both cutting approaches, however, do not take advantage of joint cutting, i.e., identifying common gate groups and cutting them jointly for a reduced overhead. This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy, enabling more efficient circuit decompositions. Moreover, our approach incorporates joint cutting via a novel gate grouping technique, further reducing sampling overhead. By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits, also providing diagnostic feedback on whether circuits are suitable for cutting.
The current noisy intermediate-scale quantum (NISQ) era is characterized by substantial errors and noise, which limit the practical feasibility of deep, many-qubit circuits. To address these constraints, quantum circuit cutting has emerged as a promising tool. Recently, there has been significant research on methods for performing such cutting effectively. In this work, the duality between quantum circuits and classical graphs - specifically, directed acyclic graphs (dags) - is leveraged to analyze the complexity of finding an optimal circuit-cutting configuration that minimizes the number of cuts. After developing a rigorous graph-theoretic framework, the complexity of identifying cut locations that partition a given quantum circuit into smaller fragments is characterized. The corresponding graph-combinatorial task is then defined, and the resulting partition problem is shown to be NP-complete. Furthermore, even a simplified version of the problem, restricted to circuits composed only of one- and two-qubit gates, is shown to be NP-complete. Finally, based on these constraints, an algorithm grounded in satisfiability modulo theories (SMT) is proposed to find optimal cuts when the number of qubits per partition is bounded. This work therefore provides a complexity-theoretic characterization of cut placement and a practical solver for bounded-size decompositions.
Current quantum computers do not yet have the required qubit resources to meet the demands of most practical quantum algorithms. To circumvent this constraint, the practice of dividing these algorithms into parts through quantum circuit cutting has been explored. Many of these works either show exponential scaling or are far from optimal solutions. In this paper, MosaiQC is presented as a novel framework to improve upon existing circuit cutting frameworks. A hybrid warmstart with refinement optimization is used to find cutting solutions, allowing the combination of both wire and gate cuts. Additionally, MosaiQC enables hardware partitions of mixed sizes. Furthermore, the refinement stage incorporates a fast approximate quadratic assignment solver to better place hardware partitions, demonstrating a mean local fidelity improvement of 19.56%±6.17% over the baseline algorithm. In runtime and sampling overhead costs, improvements of 2.88× and an average of 16.84% cut reduction (resulting in an average 5.83⋅1011× overhead reduction) are observed. MosaiQC demonstrates a superior trade-off for run speed and solution quality, while adding fundamental features excluded by most competitors. With this, MosaiQC demonstrates that scalable heuristic optimization can substantially reduce the computational overhead of circuit-cut placement for increasingly large quantum circuits.
Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.
Noisy intermediate-scale quantum (NISQ) devices with limited qubit count and connectivity limit the scale of quantum circuits that can be executed. Circuit cutting methods simulate larger quantum computers by decomposing large circuits into small subcircuits that can be executed on NISQ hardware. Existing circuit cutting methods only consider the qubit count of the target hardware for finding the locations of cuts on the circuits. This can result in deeper subcircuits after mapping on the hardware. Fidelity decays exponentially with circuit depth and diminishes the quality of execution. We propose a circuit-cutting framework that reduces variance in the depth of subcircuits after mapping to the hardware. Our method formulates the initial circuit cutting as a multi-objective optimization problem based on an evolutionary search method with the number of cuts and the maximum depth of individual routed subcircuits as fitness objectives. This method is implemented as an extension to the existing Qiskit Circuit Cutting Addon, which allows for integration in existing flows. Our approach achieves reductions in routed subcircuit depth of up to 9.9% across benchmark circuits compared with baseline methods.
Quantum Approximate Optimization Algorithms (QAOA) have demonstrated a strong potential in addressing graph-based optimization problems. However, the execution of large-scale quantum circuits remains constrained by the limitations of current quantum hardware. In this work, we introduce QuantCut, an automatic framework for circuit cutting that enables efficient execution of large quantum circuits by decomposing entangling two-qubit gates into manageable sub-circuits. Specifically, we focus on gate-cutting techniques. We apply QuantCut to a 71-qubit QAOA circuit ansatz for portfolio diversification in the S&P 500 stock market, aiming to maximize asset diversification. Our approach iteratively optimizes the expectation value while leveraging circuit-cutting strategies to reduce the qubit register size. To validate our framework, we first conduct experiments on a toy model using quantum noise simulations for the Max-Cut problem, analyzing performance improvements with an increasing number of layers. Subsequently, we extend our methodology to a real-world financial optimization scenario, showing competitive results. The results suggest that QuantCut effectively facilitates large-scale quantum computations with circuit-cutting technologies.