Modeling Quantum Volume Using Randomized Benchmarking of Room-Temperature NV Center Quantum Registers
Tom Jaeger, Minsik Kwon, Keller, Max, Maier, Rouven, Nicholas T. Bronn, Regina Finsterhoelzl, Guido Burkard, Buettner, Leon, Rebekka Eberle, D. Hähnel, Vadim Vorobyov, Jörg Wrachtrup
Accurately estimating the performance of quantum hardware is crucial for comparing different platforms and predicting the performance and feasibility of quantum algorithms and applications. In this paper, we tackle the problem of benchmarking a quantum register based on the NV center in diamond operating at room temperature. We define the connectivity map as well as single qubit performance. Thanks to an all-to-all connectivity the 2 and 3 qubit gates performance is promising and competitive among other platforms. We experimentally calibrate the error model for the register and use it to estimate the quantum volume, a metric used for quantifying the quantum computational capabilities of the register, of 8. Our results pave the way towards the unification of different architectures of quantum hardware and evaluation of the joint metrics.
Accurately estimating the performance of quantum hardware is crucial for comparing different platforms and predicting the performance and feasibility of quantum algorithms and applications. In this paper, we tackle the problem of benchmarking a quantum register based on the NV center in diamond operating at room temperature. We define the connectivity map as well as single qubit performance. Thanks to an all-to-all connectivity the 2 and 3 qubit gates performance is promising and competitive among other platforms. We experimentally calibrate the error model for the register and use it to estimate the quantum volume, a metric used for quantifying the quantum computational capabilities of the register, of 8. Our results pave the way towards the unification of different architectures of quantum hardware and evaluation of the joint metrics.
Accurately estimating the performance of quantum hardware is crucial for comparing different platforms and predicting the performance and feasibility of quantum algorithms and applications. In this paper, we tackle the problem of benchmarking a quantum register based on the NV center in diamond operating at room temperature. We define the connectivity map as well as single-qubit performance. Thanks to an all-to-all connectivity, the 2 and 3-qubit gates performance is promising and competitive among other platforms. We experimentally calibrate the error model for the register and use it to estimate the quantum volume, a metric used for quantifying the quantum computational capabilities of the register, of 8. Our results pave the way towards the unification of different architectures of quantum hardware and the evaluation of the joint metrics.
As quantum processors grow, new performance benchmarks are required to capture the full quality of the devices at scale. While quantum volume is an excellent benchmark, it focuses on the highest quality subset of the device and so is unable to indicate the average performance over a large number of connected qubits. Furthermore, it is a discrete pass/fail and so is not reflective of continuous improvements in hardware nor does it provide quantitative direction to large-scale algorithms. For example, there may be value in error mitigated Hamiltonian simulation at scale with devices unable to pass strict quantum volume tests. Here we discuss a scalable benchmark which measures the fidelity of a connecting set of two-qubit gates over N qubits by measuring gate errors using simultaneous direct randomized benchmarking in disjoint layers. Our layer fidelity can be easily related to algorithmic run time, via γ defined in Ref.\cite{berg2022probabilistic} that can be used to estimate the number of circuits required for error mitigation. The protocol is efficient and obtains all the pair rates in the layered structure. Compared to regular (isolated) RB this approach is sensitive to crosstalk. As an example we measure a N=80(100) qubit layer fidelity on a 127 qubit fixed-coupling "Eagle" processor (ibm\_sherbrooke) of 0.26(0.19) and on the 133 qubit tunable-coupling "Heron" processor (ibm\_montecarlo) of 0.61(0.26). This can easily be expressed as a layer size independent quantity, error per layered gate (EPLG), which is here 1.7×10−2(1.7×10−2) for ibm\_sherbrooke and 6.2×10−3(1.2×10−2) for ibm\_montecarlo.
Quantum volume (QV) is a widely recognized metric for assessing the practical capabilities of quantum computers, as it provides an estimate of the largest quantum circuit that can be reliably executed. However, measuring QV on a real device requires comparing experimental outcomes with ideal theoretical results—a process that rapidly becomes computationally expensive. By examining the cumulative impact of errors in two-qubit gates, we present a simple, accessible `rule of thumb’ that relates the quantum volume directly to the average error rate of native gates. Our formula shows a strong agreement with experimental data from leading quantum computing platforms, including both superconducting and trapped-ion systems. This straightforward model offers a clear, intuitive guideline for predicting quantum hardware performance, enabling more informed decisions regarding circuit design and resource allocation.
This work investigates the applicability of the nitrogen-vacancy (NV) defect center in diamond for quantum computation and metrology purposes. The NV center is a molecule like defect in the diamond lattice which is optically active and possesses an electron spin in its ground state. The spin can be used as a quantum bit and as a field sensor. The NV center has three major properties enabling individual control of single defects. Its optical properties depend on the spin state, the spin can be polarized optically and the spin state has an exceptionally long lifetime. Single NV centers can be controlled by optical and microwave radiation. Generally, the research on individually controllable quantum systems is not only motivated by quantum computation and communication. With the ongoing miniaturization nowadays electronic and electro-optic devices will soon reach the limit of single quantum building blocks. While in these applications the full complexity of single quantum systems might not be needed, small sensors based on single atoms or molecules might very well take advantage of the susceptibility of quantum coherences to environmental conditions. Major challenges for all approaches towards single quantum system control are the individual addressing, the measurement of the quantum state and the protection of quantum coherence from environmental noise. Today, there is a variety of systems (including the NV center) that allow control on the single quantum level. These are for example single photons, single ions and atoms in traps, single spins in semiconductors or single molecules in solid state systems. Rather mesoscopic examples are superconducting devices, nanomechanical oscillators or surface plasmon polaritons. Regarding the NV center it has been shown that the magnetic moment of its electron spin allows individual sensing and coupling to other surrounding electron and nuclear spins. Especially single nuclear spins were shown to be exceptional quantum memories. In this work small quantum registers of up to 5 spins have been used to test major requirements for a feasible quantum processor. Therefore, mainly artificially created high purity diamond samples with controlled spin and impurity concentration were used. The NV centers were either grown in or created via ion implantation techniques in a controlled fashion. As a first requirement for quantum computation entanglement among up to three spins has been generated and was verified by quantum state tomography. This proves the access of the full Hilbert space. Especially, entanglement among nuclear spins was very long-living. In further experiments this processor was used for first quantum algorithms like super-dense coding and the Deutsch algorithm. In addition, this work demonstrates new methods to initialize nuclear spin qubits into a desired quantum state. This is particularly important as improper initialization inhibits quantum computation. One of these methods is related to dynamic nuclear spin polarization and the other to measurement based state preparation. Nuclear spins in the diamond lattice originate mainly from the C-13 isotope. By artificially altering its content the influence on the NV center spin was investigated. The coherence times of the NV center were increasing inversely with the nuclear spin density. Even increasing nuclear spin density to offer more nuclear spin qubits to an operational quantum register was possible. As an alternative route of scaling up the quantum register pairs of closely spaced NV centers were investigated. For the first time two qubit gates among two NV centers mediated by magnetic dipolar coupling have been realized. Furthermore the sensing ability was demonstrated by measuring the relative distance of the two centers (10 nm) with sub-nm precision. Eventually, this work contains new insight into the electronically excited state of the NV center which allowed a more advanced control of the electron and nuclear spins. A comparably high magnetic field was used to decouple electron and nuclear spins. Finally, this allowed quantum nondemolition measurements on single nuclear spins which manifests in the observation of quantum jumps. The new insight was used to drastically improve the performance of quantum state readout. Summarizing, it was shown that single NV centers and proximal nuclear spins form versatile small quantum registers which can be interconnected with neighboring such NV quantum registers. Although the number of qubits used in this work is still small the experimental results propose a way of how to proceed when building a quantum computer. Regarding quantum metrology, however, the use of such a small register which can sense fields and store and process the results would already outperform a single NV electron spin by orders of magnitude.
Various benchmarking metrics have been developed to quantify the performance of quantum computing hardware and help evaluate development. However, it is not always necessary to know the metric values precisely. This is especially true for potential end-users who may not be experts in the underlying technology itself. In this work, we show how to estimate the quantum volumetric metrics defined in Ref. [1] based on system parameters such as qubit number, qubit layout/connectivity, and physical error rates. As part of this work, we also include an initial analysis of how the overhead required for quantum error correction in systems below the error correction viability threshold affects the metric value of that system.
As quantum computers grow in size and scope, a question of great importance is how best to benchmark performance. Here we define a set of characteristics that any benchmark should follow -- randomized, well-defined, holistic, device independent -- and make a distinction between benchmarks and diagnostics. We use Quantum Volume (QV) [1] as an example case for clear rules in benchmarking, illustrating the implications for using different success statistics, as in Ref. [2]. We discuss the issue of benchmark optimizations, detail when those optimizations are appropriate, and how they should be reported. Reporting the use of quantum error mitigation techniques is especially critical for interpreting benchmarking results, as their ability to yield highly accurate observables comes with exponential overhead, which is often omitted in performance evaluations. Finally, we use application-oriented and mirror benchmarking techniques to demonstrate some of the highlighted optimization principles, and introduce a scalable mirror quantum volume benchmark. We elucidate the importance of simple optimizations for improving benchmarking results, and note that such omissions can make a critical difference in comparisons. For example, when running mirror randomized benchmarking, we observe a reduction in error per qubit from 2% to 1% on a 26-qubit circuit with the inclusion of dynamic decoupling.