Spin qubits in quantum dots provide a promising platform for realizing large-scale quantum processors since they have a small characteristic size of a few tens of nanometers. One difficulty of controlling, e.g., a few thousand qubits on a single chip is the large number of control lines. The crossbar control architecture has been proposed to reduce the number of control lines exploiting shared control among the qubits. Here we compile the surface code cycle to a pulse sequence that can be executed in the crossbar architecture. We decompose the quantum circuits of the stabilizer measurements in terms of native gates of the spin-qubit architecture. We provide a routing and scheduling protocol and construct a gate voltage pulse sequence for the stabilizer measurement cycle. During this protocol, coherent phase errors can occur on idle qubits, due to the operational constraints of the crossbar architecture. We characterize these crosstalk errors during the stabilizer measurement cycle and identify an experimentally relevant parameter regime where the crosstalk errors are below the surface code threshold. Our results provide design guidelines for near-term qubit experiments with crossbar architectures.
Spin qubits in quantum dots provide a promising platform for realizing large-scale quantum processors since they have a small characteristic size of a few tens of nanometers. One difficulty of controlling, e.g., a few thousand qubits on a single chip is the large number of control lines. The crossbar control architecture has been proposed to reduce the number of control lines exploiting shared control among the qubits. Here we compile the surface code cycle to a pulse sequence that can be executed in the crossbar architecture. We decompose the quantum circuits of the stabilizer measurements in terms of native gates of the spin-qubit architecture. We provide a routing and scheduling protocol and construct a gate voltage pulse sequence for the stabilizer measurement cycle. During this protocol, coherent phase errors can occur on idle qubits, due to the operational constraints of the crossbar architecture. We characterize these crosstalk errors during the stabilizer measurement cycle and identify an experimentally relevant parameter regime where the crosstalk errors are below the surface code threshold. Our results provide design guidelines for near-term qubit experiments with crossbar architectures.
This notebook contains a verification algorithm for adiabatic qubit shuttling-based routing in the shared-control crossbar architecture, which is used in the manuscript 'Compiling the surface code to crossbar spin qubit architectures'. As inputs, one needs to specify (i) the desired movements of the electrons (qubits) in the array, and (ii) the abstract pulse sequence specifying the gate-voltage changes. Then, the algorithm verifies whether the abstract pulse sequence generates the desired movements. For an L×L crossbar array, assuming periodic boundary conditions, abstract plunger gate voltage values are expected as a list of integer values with length L. This version of the code can handle up to L=13 different plunger gate voltages (implying a unit cell size L×L=13×13), since we use lowercase characters to enumerate the (vertical and horizontal) barrier gates.
Abstract A central challenge for the scaling of quantum computing systems is the need to control all qubits in the system without a large overhead. A solution for this problem in classical computing comes in the form of so-called crossbar architectures. Recently we made a proposal for a large-scale quantum processor (Li et al arXiv:1711.03807 (2017)) to be implemented in silicon quantum dots. This system features a crossbar control architecture which limits parallel single-qubit control, but allows the scheme to overcome control scaling issues that form a major hurdle to large-scale quantum computing systems. In this work, we develop a language that makes it possible to easily map quantum circuits to crossbar systems, taking into account their architecture and control limitations. Using this language we show how to map well known quantum error correction codes such as the planar surface and color codes in this limited control setting with only a small overhead in time. We analyze the logical error behavior of this surface code mapping for estimated experimental parameters of the crossbar system and conclude that logical error suppression to a level useful for real quantum computation is feasible.
Despite Noisy Intermediate-Scale Quantum devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not so much attention has been paid to mapping and compilation implementations for spin-qubit quantum processors due to the scarce availability of experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring solutions on such devices. In this work, we discuss the unique mapping challenges of a scalable crossbar architecture with shared control and introduce SpinQ , the first native compilation framework for scalable spin-qubit architectures. At the core of SpinQ is the Integrated Strategy that addresses the unique operational constraints of the crossbar while considering compilation scalability and obtaining a O(n) computational complexity. To evaluate the performance of SpinQ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping techniques that could increase algorithm success rates on this architecture and potentially inspire further research on quantum circuit mapping for other scalable spin-qubit architectures.
Spin qubits in silicon quantum dots are one of the most promising building blocks for large scale quantum computers thanks to their high qubit density and compatibility with the existing semiconductor technologies. High fidelity single-qubit gates exceeding the threshold of error correction codes like the surface code have been demonstrated, while two-qubit gates have reached 98% fidelity and are improving rapidly. However, there are other types of error --- such as charge leakage and propagation --- that may occur in quantum dot arrays and which cannot be corrected by quantum error correction codes, making them potentially damaging even when their probability is small. We propose a surface code architecture for silicon quantum dot spin qubits that is robust against leakage errors by incorporating multi-electron mediator dots. Charge leakage in the qubit dots is transferred to the mediator dots via charge relaxation processes and then removed using charge reservoirs attached to the mediators. A stabiliser-check cycle, optimised for our hardware, then removes the correlations between the residual physical errors. Through simulations we obtain the surface code threshold for the charge leakage errors and show that in our architecture the damage due to charge leakage errors is reduced to a similar level to that of the usual depolarising gate noise. Spin leakage errors in our architecture are constrained to only ancilla qubits and can be removed during quantum error correction via reinitialisations of ancillae, which ensure the robustness of our architecture against spin leakage as well. Our use of an elongated mediator dots creates spaces throughout the quantum dot array for charge reservoirs, measuring devices and control gates, providing the scalability in the design.
The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. To increase the number of qubits to the thousands or millions of qubits needed for practical quantum information, we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for nonplanar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates enable qubit addressability and readout. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning-noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future.