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arXiv:2412.02036

CaliScalpel: In-Situ and Fine-Grained Qubit Calibration Integrated with Surface Code Quantum Error Correction

Xiang Fang, Keyi Yin, Yuchen Zhu, Jixuan Ruan, Dean Michael Tullsen, Zhiding Liang, Andrew T. Sornborger, Li, Ang, Travis S. Humble, Yufei Ding, Yunong Shi

Published Dec 2, 2024• 0 citations
arXivHTMLPDF

Abstract

Quantum Error Correction (QEC) is a cornerstone of fault-tolerant, large-scale quantum computing. However, qubit error drift significantly degrades QEC performance over time, necessitating periodic calibration. Traditional calibration methods disrupt quantum states, requiring system downtime and making in situ calibration infeasible. We present CaliScalpel, an innovative framework for in situ calibration in surface codes. The core idea behind CaliScalpel is leveraging code deformation to isolate qubits undergoing calibration from logical patches. This allows calibration to proceed concurrently with computation, while code enlargement maintains error correction capabilities with minimal qubit overhead. Additionally, CaliScalpel incorporates optimized calibration schedules derived from detailed device characterization, effectively minimizing physical error rates. Our results show that CaliScalpel achieves concurrent calibration and computation with modest qubit overhead and negligible execution time impact, marking a significant step toward practical in situ calibration in surface-code-based quantum computing systems.

DOI
10.48550/arxiv.2412.02036

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Quantum Error Correction (QEC) is a cornerstone of fault-tolerant, large-scale quantum computing. However, qubit error drift significantly degrades QEC performance over time, necessitating periodic calibration. Traditional calibration methods disrupt quantum states, requiring system downtime and making in situ calibration infeasible. We present CaliScalpel, an innovative framework for in situ calibration in surface codes. The core idea behind CaliScalpel is leveraging code deformation to isolate qubits undergoing calibration from logical patches. This allows calibration to proceed concurrently with computation, while code enlargement maintains error correction capabilities with minimal qubit overhead. Additionally, CaliScalpel incorporates optimized calibration schedules derived from detailed device characterization, effectively minimizing physical error rates. Our results show that CaliScalpel achieves concurrent calibration and computation with modest qubit overhead and negligible execution time impact, marking a significant step toward practical in situ calibration in surface-code-based quantum computing systems.
Quantum error correction (QEC) promises to exponentially suppress qubit noise, but typically assumes spatially-uniform and temporally-constant noise rates. However, real quantum hardware exhibits variation in noise levels over time, which will be amplified by QEC if not addressed. To mitigate this drift in error rates, we leverage transient information readily available in surface code quantum error correction to predict logical error rates (LER) in real time. We infer a prediction model by sampling physical error rates from real hardware, and mapping detector fire rate (DFR), or parity of stabilizer measurements across QEC rounds, to LER. This allows for on-the-fly LER predictions without the typical characterization overhead required to determine LER. This method can easily be extended to other stabilizer codes. Importantly, we observe that this prediction should be accurate yet conservative (i.e. give an upper estimate) to enable appropriately fast responses to real-time physical error changes. That is, responses should be executed marginally ahead of time to allow for their execution to complete, and minimize time spent (ideally none) above intolerable error rates. More importantly, we pair this predictor with a scheme which remaps drifted logical qubits to fresh tiles in a patch-based architecture while their original tiles are recalibrated. Our results demonstrate DFR-based prediction to be an effective LER predictor, and remapping as a spatially efficient and timely mitigation response for small code distances, both of which are significant steps in furthering practical QEC.
Quantum Error Correction (QEC) is essential for fault-tolerant, large-scale quantum computation.However, error drift in qubits undermines QEC performance during long computations, necessitating frequent calibration.Conventional calibration methods disrupt quantum states, requiring system downtime and rendering in situ calibration impractical.To address this challenge, we propose QECali, a novel framework that enables in situ calibration for surface codes.Our evaluation demonstrates that QECali introduces modest qubit overhead and negligible increases in execution time, offering the first practical solution for in situ calibration in surface code based quantum computation.
The ability to coherently and reliably manipulate quantum information marks a fundamental technological leap—realizable through a universal, fault‑tolerant quantum computer. Achieving this goal requires progress across all layers of the quantum computing stack, from physical qubits to theoretical algorithms. In this work, we address multiple layers of this stack. We develop a software architecture for scalable device calibration using modular calibration graphs. We introduce real‑time frequency stabilization techniques, demonstrating improved single‑qubit gate fidelities and progress toward multiqubit feedback. Finally, we explore how quantum error correction overhead can be reduced using low‑density parity‑check codes. We present logical protocols for a non‑local nine‑qubit code, which significantly outperforms comparable surface code implementations in both qubit efficiency and computational capability. These results represent practical steps toward overcoming key challenges in fault‑tolerant quantum computing.
This work explores the integration of Quantum Error Correction (QEC) techniques within energy-efficient green communication networks, emphasizing their pivotal role in achieving sustainability in next-generation Information and Communication Technology (ICT) systems. Quantum technologies, particularly error correction protocols like surface codes are indispensable for reliable quantum information processing. However, their implementation often incurs substantial energy overhead due to the extensive physical qubit resources required. This research proposes a framework for adapting scalable QEC algorithms, leveraging innovations such as reconfigurable atom arrays, to optimize energy consumption while preserving high fidelity in quantum operations. Surface codes, a cornerstone of QEC, encode logical qubits in two-dimensional lattices of physical qubits, utilizing stabilizer measurements to detect and correct bit-flip and phase-flip errors. The performance of surface codes is influenced by critical parameters such as code distance, which determines fault tolerance, and gate fidelity, which impacts logical error rates. Through a comprehensive analysis of these parameters, this work evaluates the interplay between code distance, qubit array size, and gate fidelity to highlight their collective impact on fault tolerance and computational accuracy. These insights align with global efforts to reduce the environmental footprint of emerging quantum technologies, advancing the principles of green ICT and environmentally conscious innovation.
Surface-code quantum error correction (QEC) is pivotal for fault-tolerant quantum computing, but its energy efficiency remains underexplored. This work derives a practical lower bound on the energy cost per logical-qubit operation, accounting for gate-fidelity decay's impact on code distance and physical-qubit overhead. By modeling the energy consumption of gate operations and error correction, we express the total cost as $ E = (E_g N_g + E_c N_c)/N_l $, where $ E_g $, $ E_c $, $ N_g $, $ N_c $, and $ N_l $ represent gate and physical-qubit energy costs, gate counts, physical-qubit counts, and logical qubit counts, respectively. Gate-fidelity decay increases the required code distance $ d $, scaling $ N_c $ and thus $ E $. We propose normalizing computational cost in joules per logical-qubit operation (JPCUB), isolating logical work from error-correction overhead. Quantitative predictions for $ E_g $, $ E_c $, and $ N_c $ remain [to verify], but the functional dependence on $ d $ and gate fidelities is established. This framework informs energy-efficient QEC design and benchmarks. ## 1. Introduction Surface codes enable fault-tolerant quantum computation by encoding logical qubits in a 2D lattice of physical qubits, correcting errors through syndrome measurements. However, the energy cost per logical operation—critical for scalability—remains poorly quantified. While theoretical foundations exist (Raussendorf & Terhal, 2006; Kitaev, 2003), prior work focuses on error-correction thresholds rather than energy efficiency. Here, we address this gap by deriving a lower bound on energy cost, considering how gate-fidelity decay necessitates larger code distances $ d $, increasing physical-qubit overhead $ N_c $. This analysis connects to the joules-per-compute (JPCUB) benchmark, advocating for energy normalization per logical qubit to disentangle computational work from error-correction costs. ## 2. Background Surface codes encode logical qubits using a 2D grid of
Quantum Error Correction (QEC) is essential for future quantum computers due to its ability to exponentially suppress physical errors. The surface code is a leading error-correcting code candidate because of its local topological structure, experimentally achievable thresholds, and support for universal gate operations with magic states. However, its physical overhead scales quadratically with number of correctable errors. Conversely, quantum low-density parity-check (qLDPC) codes offer superior scaling but lack, on their own, a clear path to universal logical computation. Therefore, it is becoming increasingly evident is becoming that there are significant advantages to designing architectures using multiple codes. Heterogeneous architectures provide a clear path to universal logical computation as well as the ability to access different resource trade offs. To address this, we propose integrating the surface code and gross code using an ancilla bus for inter-code data movement. This approach involves managing trade-offs, including qubit overhead, a constrained instruction set, and gross code (memory) routing and management. While our focus is on the gross-surface code architecture, our method is adaptable to any code combination and the constraints generated by that specific architecture. Motivated by the potential reduction of physical qubit overhead, an ever important feature in the realization of fault tolerant computation, we perform the first full system study of heterogeneous error-correcting codes, discovering architectural trade-offs and optimizing around them. We demonstrate physical qubit reductions of up to 6.42x when executing an algorithm to a specific logical error rate, at the cost of up to a 3.43x increase in execution time.