Implementing many important sub-circuits on near-term quantum devices remains a challenge due to the high levels of noise and the prohibitive depth on standard nearest-neighbour topologies. Overcoming these barriers will likely require quantum error mitigation (QEM) strategies. This work introduces the notion of efficient, high-fidelity verifier circuit architectures that we propose for use in such a QEM scheme. We provide a method for constructing verifier circuits for any quantum circuit that is accurately represented by a low-dimensional matrix product operator (MPO). We demonstrate our method by constructing explicit verifier circuits for multi-controlled single unitary gates as well as the quantum Fourier transform (QFT). By transpiling the circuits to a 2D array of qubits, we estimate the crossover point where the verifier circuit is shallower than the circuit itself, and hence useful for QEM. We propose a method of in situ QEM using the verifier circuit architecture. We conclude that our approach may be useful for calibrating quantum sub-circuits to counter coherent noise but cannot correct for the incoherent noise present in current devices.
Implementing many important sub-circuits on near-term quantum devices remains a challenge due to the high levels of noise and the prohibitive depth on standard nearest-neighbour topologies. Overcoming these barriers will likely require quantum error mitigation (QEM) strategies. This work introduces the notion of efficient, high-fidelity verifier circuit architectures that we propose for use in such a QEM scheme. We provide a method for constructing verifier circuits for any quantum circuit that is accurately represented by a low-dimensional matrix product operator (MPO). We demonstrate our method by constructing explicit verifier circuits for multi-controlled single unitary gates as well as the quantum Fourier transform (QFT). By transpiling the circuits to a 2D array of qubits, we estimate the crossover point where the verifier circuit is shallower than the circuit itself, and hence useful for QEM. We propose a method of in situ QEM using the verifier circuit architecture. We conclude that our approach may be useful for calibrating quantum sub-circuits to counter coherent noise but cannot correct for the incoherent noise present in current devices.
In the era of noisy intermediate-scale quantum devices, the number of controllable hardware qubits is insufficient to implement quantum error correction.As an alternative, quantum error mitigation (QEM) can suppress errors in measurement results via repeated experiments and postprocessing of data.Typical techniques for error mitigation, e.g., the quasiprobability decomposition method, ignore correlated errors between different gates.Here, we introduce a QEM method based on the matrix product operator (MPO) representation of a quantum circuit that can characterize the noise channel with polynomial complexity.Our technique is demonstrated on a depth = 20 fully parallel quantum circuit of up to N q = 20 qubits undergoing local and global noise.The circuit error is reduced by a several-times factor with only a small bond dimension D = 1 for the noise channel.The MPO representation increases the accuracy of modeling noise without consuming more experimental resources, which improves the QEM performance and broadens its scope of application.Our method is hopeful of being applied to circuits in higher dimensions with more qubits and deeper depth.
We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.
Near-term quantum computers have been built as intermediate-scale quantum devices and are fragile against quantum noise effects, namely, NISQ devices. Traditional quantum-error-correcting codes are not implemented on such devices and to perform quantum computation in good accuracy with these machines we need to develop alternative approaches for mitigating quantum computational errors. In this work, we propose quantum error mitigation (QEM) scheme for quantum computational errors which occur due to couplings with environments during gate operations, i.e., decoherence. To establish our QEM scheme, first we estimate the quantum noise effects on single-qubit states and represent them as groups of quantum circuits, namely, quantum-noise-effect circuit groups. Then our QEM scheme is conducted by subtracting expectation values generated by the quantum-noise-effect circuit groups from those obtained by the quantum circuits for the quantum algorithms under consideration. As a result, the quantum noise effects are reduced, and we obtain approximately the ideal expectation values via the quantum-noise-effect circuit groups and the numbers of elementary quantum circuits composing them scale polynomial with respect to the products of the depths of quantum algorithms and the numbers of register bits. To numerically demonstrate the validity of our QEM scheme, we run noisy quantum simulations of qubits under amplitude damping effects for four types of quantum algorithms. Furthermore, we implement our QEM scheme on IBM Q Experience processors and examine its efficacy. Consequently, the validity of our scheme is verified via both the quantum simulations and the quantum computations on the real quantum devices. Our QEM scheme is solely composed of quantum-computational operations (quantum gates and measurements), and thus, it can be conducted by any type of quantum device. In addition, it can be applied to error mitigation for many other types of quantum noise effects as well as noisy quantum computing of long-depth quantum algorithms.
We propose using variational quantum algorithms (VQAs) to simulate established quantum algorithms under realistic noise conditions, aiming to surpass the fidelity of theoretical circuits in noisy environments. Focusing on the Quantum Fourier Transform (QFT), we perform numerical simulations for two qubits under both coherent and incoherent noise. To enhance generalization, we further introduce the use of Mutually Unbiased Bases (MUBs) during the optimization. Our results show that the variational circuit can reproduce the QFT with higher fidelity in scenarios dominated by coherent noise. This demonstrates the potential of the approach as an effective error-mitigation strategy for small- to medium-scale quantum systems, particularly in settings where coherent noise strongly impacts performance. Beyond mitigating noise and improving fidelity, the method can be adapted to the noise profile of a specific device, providing a versatile and practical route to enhance the reliability of quantum algorithms in near-term quantum hardware.
Quantum error mitigation (QEM) is typically viewed as a suite of practical techniques for today's noisy intermediate-scale quantum devices, with limited relevance once fault-tolerant quantum computers become available. In this work, we challenge this conventional wisdom by showing that QEM can continue to provide substantial benefits in the era of quantum error correction (QEC), and in an even more efficient manner than it does on current devices. We introduce a framework for logical-level QEM that leverages soft information naturally produced by QEC decoders, requiring no additional data, hardware modifications, or runtime overhead beyond what QEC protocols already provide. Within this framework, we develop and analyze three logical-level QEM techniques: post-selection and runtime abort policies, probabilistic error cancellation, and zero-noise extrapolation. Our techniques reduce logical error rates by more than 100x while discarding fewer than 0.1% of shots; they also provide in situ characterization of logical channels for QEM protocols. As a proof of principle, we benchmark our approach using a surface-code architecture and two state-of-the-art decoders based on tensor-network contraction and minimum-weight perfect matching. We evaluate logical-level QEM on random Clifford circuits and molecular simulation algorithms and find that, compared to previous approaches relying on QEC only or QEC combined with QEM, we can achieve up to 87.4% spacetime overhead savings. Our results demonstrate that logical-level QEM with QEC decoder soft information can reliably improve logical performance, underscoring the efficiency and usefulness of QEM techniques for fault-tolerant quantum computers.
Despite rapid advances in quantum hardware, noise remains a central obstacle to deploying quantum algorithms on near-term devices. In particular, random coherent errors that accumulate during circuit execution constitute a dominant and fundamentally challenging noise source. We introduce a noise-resilient framework for Quantum Signal Processing (QSP) that mitigates such coherent errors without increasing circuit depth or ancillary qubit requirements. Our approach uses ensembles of noisy QSP circuits combined with measurement-level averaging to suppress random phase errors in Z rotations. Building on this framework, we develop robust QSP algorithms for implementing polynomial functions of Hermitian matrices and for estimating observables, with applications to Hamiltonian simulation, quantum linear systems, and ground-state preparation. We analyze the trade-off between approximation error and hardware noise, which is essential for practical implementation under the stringent depth and coherence constraints of current quantum hardware. Our results establish a practical pathway for integrating error mitigation seamlessly into algorithmic design, advancing the development of robust quantum computing, and enabling the discovery of scientific applications with near- and mid-term quantum devices.