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arXiv:2411.00751 · Physical Review Research

Reshaping quantum device noise via repetition code circuits

Yue Ma, Michael Hanks, Evdokia Gneusheva, M. S. Kim

Published Aug 25, 2025• 0 citations
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Abstract

Noise of a quantum processor can be an important resource for simulating open quantum dynamics. However, this requires characterizing the device noise and then transforming it into a target structure. Here, we take the first step toward this goal: We analytically and numerically study reshaping the noise associated with native trapped-ion two-qubit entangling gates via quantum circuits based on repetition codes, and demonstrate our findings on the IonQ Aria-1 quantum hardware. We investigate all the building blocks, including the quantum channels describing noisy two-qubit entangling gates, the compilation of the encoding circuits into native gates, and the propagation of two-qubit errors across ideal single-qubit gates.

DOI
10.1103/16gx-m7kg

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Noise of a quantum processor can be an important resource for simulating open quantum dynamics. However, this requires characterizing the device noise and then transforming it into a target structure. Here, we take the first step toward this goal: We analytically and numerically study reshaping the noise associated with native trapped-ion two-qubit entangling gates via quantum circuits based on repetition codes, and demonstrate our findings on the IonQ Aria-1 quantum hardware. We investigate all the building blocks, including the quantum channels describing noisy two-qubit entangling gates, the compilation of the encoding circuits into native gates, and the propagation of two-qubit errors across ideal single-qubit gates.
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Readout errors are one of the dominant sources of noise in current quantum processors, limiting both expectation-value estimation and sampling-based applications. Since they affect only the classical measurement outcomes, they can be addressed using classical coding techniques: immediately before measurement, each data qubit is redundantly encoded with ancilla qubits, and the resulting bit string is decoded either by post-selection or by majority voting. Unlike conventional readout error mitigation, which corrects only aggregate quantities such as expectation values, this approach operates on individual measurement shots and can therefore produce approximately corrected samples. We present a systematic cross-platform and cross-generation experimental evaluation of repetition-code readout error detection and correction. We benchmark the same protocol on IBM Heron r1-r3 superconducting processors and Quantinuum H1 and H2 trapped-ion processors while independently varying the code distance, hardware generation, and encoding layout. We find that both error detection and correction improve readout fidelity on every device and generation tested, even as the unencoded baseline improves substantially across successive hardware releases. At the same time, the value of additional redundancy depends strongly on the underlying hardware. On superconducting processors, the extra gate errors introduced by the encoding rapidly offset its benefits, whereas on trapped-ion processors the much lower gate error rates allow larger code distances to remain advantageous.
Quantum error correction is vital for implementing universal quantum computing. A key component is the encoding circuit that maps a product state of physical qubits into the encoded multipartite entangled logical state. Known methods are typically not ``optimal'' either in terms of the circuit depth (and therefore the error burden) or the specifics of the target platform, i.e., the native gates and topology of a system. This work introduces a variational compiler for efficiently finding the encoding circuit of general quantum error-correcting codes with given quantum hardware. Focusing on the noisy intermediate-scale quantum regime, we show how to systematically compile the circuit following an optimizing process seeking to minimize the number of noisy operations that are allowed by the noisy quantum hardware or to obtain the highest fidelity of the encoded state with noisy gates. We demonstrate our method by deriving efficient encoders for logic states of the five-qubit code and the seven-qubit Steane code. We describe ways to augment the discovered circuits with error detection. Our method is applicable quite generally for compiling the encoding circuits of quantum error-correcting codes.
Abstract Quantum noise in real-world devices poses a significant challenge in achieving practical quantum advantage, since accurately compiled and executed circuits are typically deep and highly susceptible to decoherence. To facilitate the implementation of complex quantum algorithms on noisy hardware, we propose an approximate method for compiling target quantum circuits into brick-wall layouts. This new circuit design consists of two-qubit CNOT gates that can be directly implemented on real quantum computers, in conjunction with optimized one-qubit gates, to approximate the essential dynamics of the original circuit while significantly reducing its depth. Our approach is evaluated through numerical simulations of time-evolution circuits for the critical Ising model, quantum Fourier transformation, and Haar-random quantum circuits, as well as experiments on IBM quantum platforms. By accounting for compilation error and circuit noise, we demonstrate that time evolution and quantum Fourier transformation circuits achieve high compression rates, while random quantum circuits are less compressible. The degree of compression is related to the rate of entanglement accumulation in the target circuit. In particular, experiments on IBM platforms achieve a compression rate of 12.512.512.5 for N=12N=12N=12, significantly extending the application of current quantum devices. Furthermore, large-scale numerical simulations for system sizes up to N=30N=30N=30 reveal that the optimal depth dmaxd_{\rm max}dmax​ to achieve maximal overall fidelity is independent of system size NNN, suggesting the scalability of our method for large quantum devices in terms of quantum resources.
We present a method for estimating QEC circuit-level noise levels assuming that only single-shot measurements are available (e.g. measurements are slow and performed in a zoned/parallel fashion), and that lower level quantum hardware calibration is not possible (e.g. cloud access) or not feasible (e.g. large scale computing). We develop and run surface code plaquette experiments using two syndrome qubit configurations: FRESH, involving fresh qubits for each plaquette repetition, and RECYCLE, reusing qubits. To validate our approach, we compile plaquettes to ion-trap (IonQ Aria1) native gate set and apply hardware-aware rewrite templates to reduce circuit depth and execution time. We also run the experiments on a non-shuttling, superconducting processor (IBM Torino). We estimate circuit-level noise rates from the resulting single-shot plaquette measurement statistics, and conclude numerically about the viability of low-depth QEC experiments.