Noise-aware circuit compilations for a continuously parameterized two-qubit gateset
Christopher G. Yale, Rich Rines, Victory Omole, Bharath Thotakura, Ashlyn D. Burch, Matthew N. H. Chow, Megan Ivory, Daniel Lobser, Brian McFarland, Melissa Revelle, Susan Clark, Pranav Gokhale
State-of-the-art noisy-intermediate-scale quantum processors are currently implemented across a variety of hardware platforms, each with their own distinct gatesets. As such, circuit compilation should not only be aware of but also deeply connect to the native gateset and noise properties of each. Trapped-ion processors are one such platform that provides a gateset that can be continuously parameterized across both one- and two-qubit gates. Here we use the Quantum Scientific Computing Open User Testbed to study noise-aware compilations focused on continuously parameterized two-qubit Z Z gates (based on the Mølmer-Sørensen interaction) using , a quantum software platform for hardware-aware circuit compiler optimizations. We discuss the realization of Z Z gates with arbitrary angle on the all-to-all connected trapped-ion system. Then we discuss a variety of different compiler optimizations that innately target these Z Z gates and their noise properties. These optimizations include moving from a restricted maximally entangling gateset to a continuously parameterized one, swap mirroring to further reduce the total entangling angle of the operations, focusing the heaviest Z Z angle participation on the best-performing gate pairs, and circuit approximation to remove the least impactful Z Z gates. We demonstrate these compilation approaches on the hardware with randomized quantum volume circuits, observing the potential to realize a larger quantum volume as a result of these optimizations. Using differing yet complementary analysis techniques, we observe the distinct improvements in system performance provided by these noise-aware compilations and study the role of stochastic and coherent error channels for each compilation choice.
State-of-the-art noisy-intermediate-scale quantum processors are currently implemented across a variety of hardware platforms, each with their own distinct gatesets. As such, circuit compilation should not only be aware of but also deeply connect to the native gateset and noise properties of each. Trapped-ion processors are one such platform that provides a gateset that can be continuously parameterized across both one- and two-qubit gates. Here we use the Quantum Scientific Computing Open User Testbed to study noise-aware compilations focused on continuously parameterized two-qubit Z Z gates (based on the Mølmer-Sørensen interaction) using , a quantum software platform for hardware-aware circuit compiler optimizations. We discuss the realization of Z Z gates with arbitrary angle on the all-to-all connected trapped-ion system. Then we discuss a variety of different compiler optimizations that innately target these Z Z gates and their noise properties. These optimizations include moving from a restricted maximally entangling gateset to a continuously parameterized one, swap mirroring to further reduce the total entangling angle of the operations, focusing the heaviest Z Z angle participation on the best-performing gate pairs, and circuit approximation to remove the least impactful Z Z gates. We demonstrate these compilation approaches on the hardware with randomized quantum volume circuits, observing the potential to realize a larger quantum volume as a result of these optimizations. Using differing yet complementary analysis techniques, we observe the distinct improvements in system performance provided by these noise-aware compilations and study the role of stochastic and coherent error channels for each compilation choice.
Continuously parameterized two-qubit gates are a key feature of state-of-the-art trapped-ion quantum processors as they have favorable error scalings and show distinct improvements in circuit performance over more restricted maximally entangling gatesets. In this work, we provide a comprehensive and pedagogical discussion on how to practically implement these continuously parameterized Mølmer Sørensen gates on the Quantum Scientific Computing Open User Testbed (QSCOUT), a low-level trappedion processor. To generate the arbitrary entangling angles, θ, we simply scale the amplitude of light used to generate the entanglement. However, doing so requires careful consideration of amplifier saturation as well as the variable light shifts that result. As such, we describe a method to calibrate and cancel the dominant fourth-order effects, followed by a dynamic virtual phase advance during the gate to cancel any residual light shifts, and find a linear scaling between θ and the residual light shift. Once, we have considered and calibrated these effects, we demonstrate performance improvement with decreasing θ. Finally, we describe nuances of hardware control to transform the XX-type interaction of the arbitraryangle Mølmer-Sørensen gate into a phase-agnostic and crosstalk-mitigating ZZ interaction.
Abstract Compiling quantum circuits to account for hardware restrictions is an essential part of the quantum computing stack. Circuit compilation allows us to adapt algorithm descriptions into a sequence of operations supported by real quantum hardware, and has the potential to significantly improve their performance when optimisation techniques are added to the process. One such optimisation technique is reducing the number of quantum gates that are needed to execute a circuit. For instance, methods for reducing the number of non-Clifford gates or CNOT gates from a circuit are an extensive research area that has gathered significant interest over the years. For certain hardware platforms such as trapped-ion quantum computers, we can leverage some of their special properties to further reduce the cost of executing a quantum circuit in them. In this work we use global interactions, such as the Global Mølmer–Sørensen (MS) gate present in trapped-ion hardware, to optimise and synthesise quantum circuits. We design and implement an algorithm that is able to compile an arbitrary quantum circuit into another circuit that uses global gates as the entangling operation, while optimising the number of global interactions needed. The algorithm is based on the ZX -calculus and uses a specialised circuit extraction routine that groups entangling gates into Global MS gates. We benchmark the algorithm in a variety of circuits, and show how it improves their performance under state-of-the-art hardware considerations in comparison to a naive algorithm and the Qiskit optimiser.
Abstract Quantum simulation on noisy intermediate-scale quantum (NISQ) hardware is limited by short coherence time and gate errors. We present a universal variational compilation optimization method (VCOM) that directly leverages the native gate set of trapped-ion processors, namely single-qubit rotations and global Ising-type XX interactions, to construct shallow circuits for simulating molecular Hamiltonians. Specifically, VCOM employs a hybrid optimization strategy combining genetic algorithms with gradient-based refinement to compile Pauli string evolution operators e −i Pt , thereby substantially reducing circuit depth and multi-qubit gate overhead in Hamiltonian simulation. Applied to hydrogen chains, the compiled circuits achieve fidelities comparable to standard decompositions while reducing the proportion of two-qubit operations to only 1.9%–4.6% of the total native gates, a significant improvement over the standard second-order Trotter–Suzuki product formula. Under experimentally motivated laser-intensity and phase-noise models, the proposed scheme maintains high fidelity and exhibits significantly slower degradation than direct native gate decompositions of conventional circuits. These results establish native-gate-based variational compilation as a scalable and practical approach for digital quantum simulation on trapped-ion platforms, with potential extensions to strongly correlated systems and non-equilibrium dynamics.
Abstract As quantum processors grow in scale and reliability, the need for efficient quantum gate decomposition of circuits to a set of specific available gates, becomes ever more critical. The decomposition of a particular algorithm into a sequence of these available gates is not unique. Thus, the fidelity of an algorithm’s implementation can be increased by choosing an optimized decomposition. This is true both for noisy intermediate-scale quantum platforms as well as for implementation of quantum error correction schemes. Here we present a compilation scheme which implements a general-circuit decomposition to a sequence of Ising-type, long-range, multi-qubit (MQ) entangling gates, that are separated by layers of single qubit rotations. We use trapped ions as an example in which MQ gates naturally arise, yet any system that has connectivity beyond nearest-neighbors may gain from our approach. We evaluate our methods using the quantum volume (QV) test over N qubits. In this context, our method replaces 3 N 2 / 2 two-qubit gates with 2 N + 1 MQ gates. Furthermore, our method minimizes the magnitude of the entanglement phases, which typically enables an improved implementation fidelity, by using weaker driving fields or faster realizations. We numerically test our compilation and show that, compared to conventional realizations with sequential two-qubit gates, our compilations improves the logarithm of QV by 20% to 25%.
We develop new approximate compilation schemes that significantly reduce the expense of compiling the Quantum Approximate Optimization Algorithm (QAOA) for solving the Max-Cut problem. Our main focus is on compilation with trapped-ion simulators using Pauli- X operations and all-to-all Ising Hamiltonian H Ising evolution generated by Molmer-Sorensen or optical dipole force interactions, though some of our results also apply to standard gate-based compilations. Our results are based on principles of graph sparsification and decomposition; the former reduces the number of edges in a graph while maintaining its cut structure, while the latter breaks a weighted graph into a small number of unweighted graphs. Though these techniques have been used as heuristics in various hybrid quantum algorithms, there have been no guarantees on their performance, to the best of our knowledge. This work provides the first provable guarantees using sparsification and decomposition to improve quantum noise resilience and reduce quantum circuit complexity. For quantum hardware that uses edge-by-edge QAOA compilations, sparsification leads to a direct reduction in circuit complexity. For trapped-ion quantum simulators implementing all-to-all H I s i n g pulses, we show that for a ( 1 − ϵ ) factor loss in the Max-Cut approximation ( ϵ > 0 ) , our compilations improve the (worst-case) number of H I s i n g pulses from O ( n 2 ) to O ( n log ( n / ϵ ) ) and the (worst-case) number of Pauli- X bit flips from O ( n 2 ) to O ( n log ( n / ϵ ) ϵ 2 ) for n -node graphs. This is an asymptotic improvement for any constant ϵ > 0 . We demonstrate that significant improvements to the approximation ratio are obtained using decomposition in simulated trapped-ion experiments with dephasing noise. We further present a generic argument showing that sparsification results in an exponentially improved circuit fidelity lower bound in digital computing schemes based on one- and two-qubit gates, which are relevant to a wide variety of hardwares such as superconducting qubits and certain neutral atom or trapped ion setups, and more sophisticated noise models. We anticipate these approximate compilation techniques will be useful tools in a variety of future quantum computing experiments.
Ion trap quantum hardware promises to provide a computational advantage over classical computing for specific problem spaces while also providing an alternative hardware implementation path to cryogenic quantum systems as typified by IBM's quantum hardware. However, programming ion trap systems currently requires both strategies to mitigate high levels of noise and also tools to ease the challenge of programming these systems with pulse- or gate-level operations. This work focuses on improving the state-of-the-art for quantum programming of ion trap testbeds through the use of a quantum language specification, QCOR, and by demonstrating multi-level optimizations at the language, intermediate representation, and hardware backend levels. We implement a new QCOR/XACC backend to target a general ion trap testbed and then demonstrate the usage of multi-level optimizations to improve circuit fidelity and to reduce gate count. These techniques include the usage of a backend-specific numerical optimizer and physical gate optimizations to minimize the number of native instructions sent to the hardware. We evaluate our compiler backend using several QCOR benchmark programs, finding that on present testbed hardware, our compiler backend maintains the number of two-qubit native operations but decreases the number of single-qubit native operations by 1.54 times compared to the previous compiler regime. For projected testbed hardware upgrades, our compiler sees a reduction in two-qubit native operations by 2.40 times and one-qubit native operations by 6.13 times.