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arXiv:2410.16382

Runtime Reduction in Linear Quantum Charge-Coupled Devices using the Parity Flow Formalism

Domínguez, Federico, Fellner, Michael, Berend Klaver, Stefan Rombouts, Christian Ertler, Wolfgang Lechner

Published Oct 21, 2024• 0 citations
arXivHTMLPDF

Abstract

Using the Parity Flow formalism, we show that physical SWAP gates can be eliminated in linear hardware architectures, without increasing the total number of two-qubit operations. This has a significant impact on the execution time of quantum circuits in linear Quantum Charge-Coupled Devices (QCCDs), where SWAP gates are implemented by physically changing the position of the ions. Because SWAP gates are one of the most time-consuming operations in QCCDs, our scheme considerably reduces the runtime of the quantum Fourier transform and the quantum approximate optimization algorithm on all-to-all spin models, compared to circuits generated with standard compilers (TKET and Qiskit). While increasing the problem size (and therefore the number of qubits) typically demands longer runtimes, which are constrained by coherence time, our runtime reduction enables a significant increase in the number of qubits at a given coherence time.

DOI
10.48550/arxiv.2410.16382

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Using the Parity Flow formalism, we show that physical SWAP gates can be eliminated in linear hardware architectures, without increasing the total number of two-qubit operations. This has a significant impact on the execution time of quantum circuits in linear Quantum Charge-Coupled Devices (QCCDs), where SWAP gates are implemented by physically changing the position of the ions. Because SWAP gates are one of the most time-consuming operations in QCCDs, our scheme considerably reduces the runtime of the quantum Fourier transform and the quantum approximate optimization algorithm on all-to-all spin models, compared to circuits generated with standard compilers (TKET and Qiskit). While increasing the problem size (and therefore the number of qubits) typically demands longer runtimes, which are constrained by coherence time, our runtime reduction enables a significant increase in the number of qubits at a given coherence time.
We present a formalism based on tracking the flow of parity quantum information to implement algorithms on devices with limited connectivity without qubit overhead, SWAP operations, or shuttling. Instead, we leverage the fact that entangling gates not only manipulate quantum states but can also be exploited to transport quantum information. We demonstrate the effectiveness of this method by applying it to the quantum Fourier transform (QFT) and the quantum approximate optimization algorithm (QAOA) with n qubits. This improves upon all state-of-the-art implementations of the QFT on a linear nearest-neighbor architecture, resulting in a total circuit depth of 5 n − 3 and requiring n 2 − 1 gates. For the QAOA, our method outperforms SWAP networks, which are currently the most efficient implementation of the QAOA on a linear architecture. We further demonstrate the potential to balance qubit count against circuit depth by implementing the QAOA on twice the number of qubits using bilinear connectivity, which approximately halves the circuit depth.
The Quantum Charge-Coupled Device (QCCD) architecture is a modular design to expand trapped-ion quantum computer that relies on the coherent shuttling of qubits across an array of segmented electrodes.Leveraging trapped ions for their long coherence times and high-fidelity quantum operations, QCCD technology represents a significant advancement toward practical, large-scale quantum processors.However, shuttling increases thermal motion and consistently necessitates qubit swaps, significantly extend execution time and negatively affect application success rates.In this paper, we introduce S-SYNC -a compiler designed to co-optimize the number of shuttling and swapping operations.S-SYNC exploits the unique properties of QCCD and incorporates generic SWAP operations to efficiently manage shuttle and SWAP counts simultaneously.Building on the static topology formulation of QCCD, we develop scheduling heuristics to enhance overall performance.Our evaluations demonstrate that our approach reduces the shuttling number by 3.69x on average and improves the success rate of quantum applications by 1.73x on average.Moreover, we apply S-SYNC to gain insights into executing applications across various QCCD topologies and to compare the trade-offs between different initial mapping methods.
Rapid progress in the physical implementation of quantum computers gave birth to multiple recent quantum machines implemented with superconducting technology. In these NISQ machines, each qubit is physically connected to a bounded number of neighbors. This limitation prevents most quantum programs from being directly executed on quantum devices. A compiler is required for converting a quantum program to a hardware-compliant circuit, in particular, making each two-qubit gate executable by mapping the two logical qubits to two physical qubits with a link between them. To solve this problem, existing studies focus on inserting SWAP gates to dynamically remap logical qubits to physical qubits. However, most of the schemes lack the consideration of time-optimality of generated quantum circuits, or are achieving time-optimality with certain constraints. In this work, we propose a theoretically time-optimal SWAP insertion scheme for the qubit mapping problem. Our model can also be extended to practical heuristic algorithms. We present exact analysis results by using our model for quantum programs with recurring execution patterns. We have for the first time discovered an optimal qubit mapping pattern for quantum fourier transformation (QFT) on 2D nearest neighbor architecture. We also present a scalable extension of our theoretical model that can be used to solve qubit mapping for large quantum circuits.
Abstract Quantum computing is currently a research hotspot in both academia and industry. The inherent parallelism of quantum computers and the resulting powerful computing power will bring new solutions to many problems that are difficult for classical computers. However, due to the limitations of technical conditions, it is difficult to achieve full direct coupling of all qubits on a quantum chip. When compiling a quantum circuit onto a physical chip, it is necessary to ensure those two-qubit gates act on pairs of directly coupled qubits by inserting SWAP gates. It will cause great additional cost when a large number of SWAP gates are inserted, leading to the execution time of quantum circuits longer. In this paper, we designed a strategy based on the business of each individual qubit to insert SWAP gates, named Busy-Qubits-Avoid Strategy. On the one hand, we try to hide the time overhead incurred by the inserted SWAP gates by exploiting the uneven distribution of quantum gates over qubits. On the other hand, we also expect the inserted SWAP gates to make as little negative impact on subsequent two-qubit gates as possible. We designed a heuristic function which take into account both of these points. Compared with Srabe and tket, we achieved a better effect. In addition, as the number of two-qubit gates increases, better optimization results will be achieved. This implies higher execution efficiency and lower decoherence error rate.
In order to achieve speedup over conventional classical computing for finding solution of computationally hard problems, quantum computing was introduced. Quantum algorithms can be simulated in a pseudo quantum environment, but implementation involves realization of quantum circuits through physical synthesis of quantum gates. This requires decomposition of complex quantum gates into a cascade of simple one qubit and two qubit gates. The methodological framework for physical synthesis imposes a constraint regarding placement of operands (qubits) and operators. If physical qubits can be placed on a grid, where each node of the grid represents a qubit then quantum gates can only be operated on adjacent qubits, otherwise SWAP gates must be inserted to convert non-Linear Nearest Neighbor architecture to Linear Nearest Neighbor architecture. Insertion of SWAP gates should be made optimal to reduce cumulative cost of physical implementation. A schedule layout generation is required for placement and routing apriori to actual implementation. In this paper, two algorithms are proposed to optimize the number of SWAP gates in any arbitrary quantum circuit. The first algorithm is intended to start with generation of an interaction graph followed by finding the longest path starting from the node with maximum degree. The second algorithm optimizes the number of SWAP gates between any pair of non-neighbouring qubits. Our proposed approach has a significant reduction in number of SWAP gates in 1D and 2D NTC architecture.
Currently, quantum computing is developing at a high speed because its high parallelism and high computing power bring new solutions to many fields. However, due to chip process technology, it is difficult to achieve full coupling of all qubits on a quantum chip, so when compiling a quantum circuit onto a physical chip, it is necessary to ensure that the two-qubit gate acts on a pair of coupled qubits by inserting swap gates. It will cause great additional cost when a large number of swap gates are inserted, leading to the execution time of quantum circuits longer. In this paper, we designed a way based on the business to insert swap gates BQA(Busy Qubits Avoid). We exploit the imbalance of the number of gates on qubits, trying to hide the overhead of swap gates. At the same time, we also expect swap gates to make as little negative impact on subsequent two-qubit gates as possible. We have designed a heuristic function that can take into account both of these points. Compared with qiskit, the execution time of the circuit optimized by our proposed method is only 0.5 times that of the qiskit compiled circuit. And when the number of two-qubit gates is large, it will achieve higher level than general conditions. This implies higher execution efficiency and lower decoherence error rate.