The Quantum Charge-Coupled Device (QCCD) architecture is a modular design to expand trapped-ion quantum computer that relies on the coherent shuttling of qubits across an array of segmented electrodes.Leveraging trapped ions for their long coherence times and high-fidelity quantum operations, QCCD technology represents a significant advancement toward practical, large-scale quantum processors.However, shuttling increases thermal motion and consistently necessitates qubit swaps, significantly extend execution time and negatively affect application success rates.In this paper, we introduce S-SYNC -a compiler designed to co-optimize the number of shuttling and swapping operations.S-SYNC exploits the unique properties of QCCD and incorporates generic SWAP operations to efficiently manage shuttle and SWAP counts simultaneously.Building on the static topology formulation of QCCD, we develop scheduling heuristics to enhance overall performance.Our evaluations demonstrate that our approach reduces the shuttling number by 3.69x on average and improves the success rate of quantum applications by 1.73x on average.Moreover, we apply S-SYNC to gain insights into executing applications across various QCCD topologies and to compare the trade-offs between different initial mapping methods.
The Quantum Charge-Coupled Device (QCCD) architecture is a modular design to expand trapped-ion quantum computer that relies on the coherent shuttling of qubits across an array of segmented electrodes.Leveraging trapped ions for their long coherence times and high-fidelity quantum operations, QCCD technology represents a significant advancement toward practical, large-scale quantum processors.However, shuttling increases thermal motion and consistently necessitates qubit swaps, significantly extend execution time and negatively affect application success rates.In this paper, we introduce S-SYNC -a compiler designed to co-optimize the number of shuttling and swapping operations.S-SYNC exploits the unique properties of QCCD and incorporates generic SWAP operations to efficiently manage shuttle and SWAP counts simultaneously.Building on the static topology formulation of QCCD, we develop scheduling heuristics to enhance overall performance.Our evaluations demonstrate that our approach reduces the shuttling number by 3.69x on average and improves the success rate of quantum applications by 1.73x on average.Moreover, we apply S-SYNC to gain insights into executing applications across various QCCD topologies and to compare the trade-offs between different initial mapping methods.
Ion trap technologies have earned significant attention as potential candidates for quantum information processing due to their long decoherence times and precise manipulation of individual qubits, distinguishing them from other candidates in the field of quantum technologies. However, scalability remains a challenge, as introducing additional qubits into a trap increases noise and heating effects, consequently decreasing operational fidelity. Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures have addressed this limitation by interconnecting multiple traps and employing ion shuttling mechanisms to transfer ions among traps. This new architectural design requires the development of novel compilation techniques for quantum algorithms, which efficiently allocate and route qubits, and schedule operations. The aim of a compiler is to minimize ion movements and, therefore, reduce the execution time of the circuit to achieve a higher fidelity. In this paper, we propose a novel approach for initial qubit placement, demonstrating enhancements of up to 50% compared to prior methods. Furthermore, we conduct a scalability analysis on two distinct QCCD topologies: a 1D-linear array and a ring structure. Additionally, we evaluate the impact of the excess capacity - i.e. the number of free spaces within a trap - on the algorithm performance.
Trapped-ion quantum computers offer high-fidelity operations, long coherence times, and all-to-all connectivity within a single trap. However, scaling to large circuits is limited by the trap's ion capacity. The QCCD architecture addresses this by enabling ion shuttling across multiple traps, but excessive shuttling increases execution time and degrades fidelity. This paper presents an improved ion-shuttling approach targeting linear QCCD architectures. Building on a state-of-the-art approach [27] for linear trapped-ion devices, our approach introduces a front-layer-based scheduling method that dynamically prioritizes executable gates, along with a novel destination trap selection method for ion-shuttling, effectively reducing unnecessary ion movements. We also present a look-ahead gate selection strategy based on the gate dependency graph, avoiding the high runtime of the gate proximity approach used in the state-of-the-art approach, especially in circuits with all-to-all communication. Our approach achieves up to a 37.67% reduction in shuttle count and up to a 74.91% reduction in compilation time compared to the state-of-the-art approach for linear trapped-ion devices on actual NISQ benchmarks and synthetic circuits. On average, our approach achieves a 16.44% reduction in shuttle count and a 30.77% reduction in compilation time across all test cases. These improvements highlight the effectiveness of our approach, particularly for actual circuits.
Trapped ions (TI) are at the forefront of quantum computing implementation, offering unparalleled coherence, fidelity, and connectivity. However, the scalability of TI systems is hampered by the limited capacity of individual ion traps, necessitating intricate ion shuttling for advanced computational tasks. The Quantum Charge-Coupled Device (QCCD) framework has emerged as a promising solution, facilitating ion mobility for universal quantum computation. Current QCCD architectures predominantly feature a linear topology, which is increasingly recognized as inefficient for complex quantum operations. Anticipating the shift towards more efficacious designs, this paper introduces an innovative quantum scheduling strategy optimized for parallel QCCD topologies. Our strategy proposes a probabilistic formula for ion movement, alongside ingenious methods for local layer generation and layer compression, yielding a significant reduction in ion shuttle times. Through simulations, we demonstrate that our strategy not only substantially outstrips the linear model but also exhibits better performance over other parallel strategies that employ greedy algorithms. This is achieved through our nuanced resolution of complexities such as traffic blocks and trap capacity limitations. The consequent reduction in shuttle operations leads to lower energy consumption and an enhancement in the quantum computer's fidelity, ultimately accelerating program execution times.
Trapped-ion quantum computers are a promising platform, offering high-quality qubits with long coherence times and high-fidelity gate operations. The Quantum Charge Coupled Device (QCCD) architecture provides a scalable blueprint by leveraging the ability to shuttle ions between distinct zones. However, realizing such architectures in practice requires software support to manage ion movement across multi-zone layouts. In this work, we propose a compilation strategy for QCCD architectures with multiple processing zones located outside a grid-type memory zone. Unlike previous approaches that treat processing zones as black-boxes, our method explicitly models their structural constraints, enabling optimized ion movement to and through them. It combines qubit partitioning with dependency-aware gate selection to reduce inter-zone shuttling while enabling simultaneous gate execution. We implemented the method in an open-source tool and empirically demonstrated its effectiveness across several QCCD layouts, laying a foundation for the compilation of multi-zone trapped-ion systems.
Trapped-ion quantum computers exhibit promising potential to provide platforms for high-quality qubits and reliable quantum computation. The quantum charge coupled device (QCCD) architecture is a leading example that offers a modular solution to enable the realization of scalable quantum computers, paving the way for practical quantum algorithms with large qubit numbers. Within these devices, ions can be shuttled (moved) throughout the trap and through different dedicated zones, e.g., a memory zone for storage and a processing zone for the actual computation. However, due to decoherence of the ions’ quantum states, the qubits lose their quantum information over time. Thus, the required time steps of shuttling operations should be minimized. In this work,1 we propose a heuristic approach to determining an efficient shuttling schedule, which orchestrates the movement operations within the device. Given a quantum algorithm and a device architecture, the proposed approach produces shuttling schedules with a close-to-minimal amount of time steps for small-size QCCD architectures. For large-scale QCCD devices, empirical evaluations show promising results with respect to quality of the solution as well as performance. An implementation of the proposed approach is publicly available as part of the open-source Munich Quantum Toolkit (MQT) athttps://github.com/cda-tum/mqt-ion-shuttler.
Trapped-ion quantum computers hold significant promise as platforms for high-quality qubits and reliable quantum computation. The Quantum Charge Coupled Device (QCCD) architecture shows potential in enabling scalable trapped-ion quantum computers through its modular design. Within QCCD devices, ions can be shuttled throughout the trap, which is divided into different dedicated zones, e.g. a memory zone for storage and a processing zone for actual computation. While the modular approach shows promise, designing a large-scale QCCD device remains challenging due to the numerous possibilities involved in designing the precise architecture of the hardware. In this work, we propose leveraging existing compilers to evaluate design choices in the development of QCCD architectures. Rather than compiling specifically for a single device, we use the compiler to explore and evaluate the execution of representative quantum circuits on various architectures. This allows for a fast assessment of different design choices, considering individual requirements and physical limitations. To validate the feasibility of this idea, we conducted a study focusing on key design decisions, including system size, junction density, processing zone positioning, and the benefits of SWAP operations within the memory zone. Based on these results, we are able to provide first recommendations and insights for the design of future QCCD architectures.