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arXiv:2407.07552 · Nano Letters

Attojoule Superconducting Thermal Logic and Memories

Hui Wang, Niels Noordzij, M. Yu. Mikhaı̆lov, Stephan Steinhauer, Thomas Descamps, Eitan Oksenberg, Val Zwiller, Iman Esmaeil Zadeh

Published Mar 10, 2025• 5 citations
arXivHTMLPDF

Abstract

High Resolution Image Download MS PowerPoint Slide Due to stringent thermal budgets in cryogenic technologies such as superconducting quantum computers and sensors, electronic building blocks that simultaneously offer low energy consumption, fast switching, low error rates, a small footprint, and simple fabrication are pivotal for large-scale devices. Here, we demonstrate a superconducting switch with attojoule switching energy, high speed (pico-second rise/fall times), and high integration density (on the order of 10 –2 μm 2 per switch). It consists of a superconducting nanochannel and a metal heater separated by an insulating silica layer. We experimentally demonstrate digital gate operations utilizing these nanostructures, such as NOT, NAND, NOR, AND, and OR gates, with a few femtojoules of energy consumption and ultralow bit error rates <10 –8 . In addition, we build energy-efficient volatile memory elements with nanosecond operation speeds and a retention time over 10 5 s. These superconducting switches open new possibilities for increasing the size and complexity of modern cryogenic technologies.

DOI
10.1021/acs.nanolett.4c06545

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High Resolution Image Download MS PowerPoint Slide Due to stringent thermal budgets in cryogenic technologies such as superconducting quantum computers and sensors, electronic building blocks that simultaneously offer low energy consumption, fast switching, low error rates, a small footprint, and simple fabrication are pivotal for large-scale devices. Here, we demonstrate a superconducting switch with attojoule switching energy, high speed (pico-second rise/fall times), and high integration density (on the order of 10 –2 μm 2 per switch). It consists of a superconducting nanochannel and a metal heater separated by an insulating silica layer. We experimentally demonstrate digital gate operations utilizing these nanostructures, such as NOT, NAND, NOR, AND, and OR gates, with a few femtojoules of energy consumption and ultralow bit error rates <10 –8 . In addition, we build energy-efficient volatile memory elements with nanosecond operation speeds and a retention time over 10 5 s. These superconducting switches open new possibilities for increasing the size and complexity of modern cryogenic technologies.
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Experimental superconducting Josephson devices being investigated for use in digital logic and memory circuits have been demonstrated to switch in the 10 to 100 picosecond (1 picosecond = 10-12 sec) range. Projections based on the operation of individual logic circuits indicate that they may surpass semiconductor circuits in very high performance CPU's. This potential is based on the fact that these circuits dissipate extremely little energy, on the order of 10 to 1000 attojoules (attojoule = 10-18 joule), while operating with subnanosecond delays. It should, therefore, be possible to package Josephson devices very densely and interconnect them by properly terminated superconducting transmission lines so that the fast switching speed of individual circuits is retained throughout large logic networks.
Experimental superconducting Josephson devices being investigated for use in digital logic and memory circuits have been demonstrated to switch in the 10 to 100 picosecond (1 picosecond = 10-12 sec) range. Projections based on the operation of individual logic circuits indicate that they may surpass semiconductor circuits in very high performance CPU's. This potential is based on the fact that these circuits dissipate extremely little energy, on the order of 10 to 1000 attojoules (attojoule = 10-18 joule), while operating with subnanosecond delays. It should, therefore, be possible to package Josephson devices very densely and interconnect them by properly terminated superconducting transmission lines so that the fast switching speed of individual circuits is retained throughout large logic networks.
The potential of a new technology, based on the superconducting Josephson tunneling effect, has been assessed for use in high-speed computer systems. Josephson tunneling circuits for memory and logic functions can be switched at sub-nanosecond delay, do not require standby power, and dissipate extremely low energy, typically less than 10-13joule during fast switching operation. High-speed circuits with high packing densities, not limited by power dissipation problems, can therefore be expected. Low thermal noise at cryogenic temperatures ensures reliable operation despite the low energy switching signal. Practically lossless signal transmission via superconducting lines can be exploited for high-speed operation even when sizeable memory and logic modules are assembled. Two random access memory modules have been designed on the basis of single device experiments. Operational characteristics leading to the conclusion that 30 Mbit capacity, less than 1 watt refrigeration requirement (at 3.6° K) and cycle times of 40 ns (in one case) and 15 ns (in the second case), can be achieved are presented.
Cryogenic (cryo) memory devices, designed to operate at/below 4 Kelvin (K) temperature, is a prime enabler of practical quantum computing systems, and superconducting (SC) electronic platforms (Figs. 1(a), (b)) [1]. The state-of-the-art quantum algorithms require many arbitrary rotations which demand a large memory to store program instructions [2]. SC qubits (used in most of the existing quantum computing systems) are highly sensitive to noise and hence, to protect the qubit states from thermal disturbances, they are placed at a few milli-Kelvin (mK) temperature. Furthermore, to preserve the integrity of the quantum states, the SC qubits undergo continuous error correction schemes, requiring extensive memory and bandwidth [2]. Superconducting electronics (SCE) (targeted towards space applications, and high-performance computing) outperforms the conventional CMOS counterparts in terms of speed and energy-efficiency (Fig. 1(c)) [3]. Decades of research efforts have given rise to three major categories (and several sub-variants) of cryo-memories based on SC, non-SC, and hybrid technologies (Fig. 2) [2], [4]–[6]. However, the existing variants suffer from one or more of the following challenges - (i) limited scalability, (ii) process complexity, (iii) bulky peripherals, (iv) array-level interference, (v) volatility, and (vi) speed incompatibility. Therefore, a scalable cryo-memory system remains elusive. To address these existing issues, here, we present a novel cryo-memory system utilizing -(i) the polarization-induced Cooper-pair [7] modulation in a ferroelectric(FE)(FE)(FE)superconducting quantum interference device (SQUID) (Fig. 3(a)) [8], and (ii) current controlledSC↔non−SCSC\leftrightarrow non-SCSC↔non−SCswitching in a heater cryotron(hTron)(hTron)(hTron)(Fig. 4) [4]. Discrete prototypes of these devices have been demonstrated recently, but their coupled interactions (which we harness in our work) were never explored before.
As we rapidly advance through the information age, the power consumed by computers, data centers, and networks grows exponentially. This has inspired a race to develop alternative low-power computational technologies. A new adiabatic configuration of a decades-old superconducting digital logic device has darted into the lead called quantum flux parametrons (QFP). QFP operate with dissipation so low that they seemingly violate the laws of thermodynamics. In just a short span of time, they have gone from simple single NOT gates to complex processors containing thousands of gates. They are fabricated from elemental niobium superconductors cooled to just a few degrees above absolute zero. However, their efficiency is so great that for large high-performance computers with several gates, the energy savings are immense. For smaller computational platforms QFPs from high-temperature superconductors (high-Tc) are highly desirable. In this work, we take the first steps towards this goal with the demonstration of a high-T C QFP shift register. Our device is fabricated using focused helium ion beam lithography where the material is modified with an ion beam at the nanoscale to directly pattern these circuits into a high-T C thin film. We validate the correct logical operation at 25 K, over 6 times higher than niobium devices with an estimated bit energy of 0.1 attoJoule at 10 GHz.