We propose an implementation of bivariate bicycle codes [S. Bravyi et al., Nature (London) 627, 778 (2024)] based on long-range Rydberg gates between stationary neutral atom qubits. An optimized layout of data and ancilla qubits reduces the maximum Euclidean communication distance needed for nonlocal parity-check operators. An optimized Rydberg gate pulse design enables $\mathsf{CZ}$ entangling operations with fidelity $\mathcal{F}>0.999$ at a distance greater than $12\phantom{\rule{0.28em}{0ex}}\textmu{}\mathrm{m}$. The combination of optimized layout and gate design leads to a quantum error correction cycle time of $\ensuremath{\sim}1.28\phantom{\rule{0.28em}{0ex}}\mathrm{ms}$ for a [[144,12,12]] code, which is nearly a factor-of-two improvement over previous designs.
We propose an implementation of bivariate bicycle codes [S. Bravyi et al., Nature (London) 627, 778 (2024)] based on long-range Rydberg gates between stationary neutral atom qubits. An optimized layout of data and ancilla qubits reduces the maximum Euclidean communication distance needed for nonlocal parity-check operators. An optimized Rydberg gate pulse design enables CZ entangling operations with fidelity F>0.999 at a distance greater than 12\textmum. The combination of optimized layout and gate design leads to a quantum error correction cycle time of \ensuremath∼1.28ms for a [[144,12,12]] code, which is nearly a factor-of-two improvement over previous designs.
Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.
Suppressing errors is the central challenge for useful large-scale quantum computing. While quantum error correction promises a viable solution to this challenge, existing codes typically suffer from trade-offs among encoding efficiency, error threshold, and hardware feasibility. Here, we introduce Cornucopia codes, a family of practical, hardware-efficient quantum low-density parity-check codes that achieve an ultra-high encoding rate exceeding 1/2 while maintaining a pseudo-threshold exceeding 0.4% under the standard circuit-level noise model. Inspired by recent affine-permutation-based code constructions and the long-range connectivity available in reconfigurable neutral-atom arrays, we adopt a structured code geometry in which the code layout, atom rearrangement, and syndrome-extraction schedule are co-designed. This structure enables nonlocal syndrome measurements through simple, parallel atom rearrangements. A complete syndrome extraction cycle measures all X- and Z-type checks in parallel with 12 entangling layers, independent of the code size. The resulting threshold is comparable to those of the surface code and bivariate bicycle codes. In particular, a single code block [[2844,1426,18]] encodes 1,426 distance-18 logical qubits, achieving an extrapolated logical error rate of 2.6×10−16 (1.9×10−31) per logical qubit per cycle, assuming the physical error rate of 0.1% (0.01%). By comparison, a bivariate bicycle code implementation would require more than 68,000 physical qubits to encode the same number of logical qubits at a comparable logical error rate. These results bring demonstrations of ultra-low-overhead quantum error correction within the reach of near-term quantum processors.
High-rate quantum low-density parity-check (qLDPC) codes can substantially reduce qubit overhead relative to surface codes, but their advantage depends on efficiently realizing nonlocal syndrome extraction. We study the [[144,12,12]] bivariate bicycle code on a neutral-atom architecture with native three-dimensional (3D) geometry, comparing planar and 3D embeddings while holding the code fixed. We characterize spatial efficiency using the logical-qubit density, defined as the number of encoded logical qubits per unit spatial footprint. Because the optical controller's field of view limits the transverse extent of an array, this metric estimates the number of logical qubits that can be accommodated within a fixed optical field of view. The 3D embedding achieves approximately 4× greater areal logical-qubit density than the planar layout and 42× greater than a surface-code baseline. It also reduces the bivariate bicycle syndrome-extraction time by roughly 2× compared to a planar baseline, with fewer movement operations and substantially shorter atom-transport distance. Native 3D geometry can improve both the packing density and executable realization of nonlocal qLDPC codes, making practical performance depend jointly on code structure, optical geometry, transport scheduling, and hardware-level noise. This motivates further development of control techniques in 3D.
High-rate quantum error correcting (QEC) codes with moderate overheads in qubit number and control complexity are highly desirable for achieving fault-tolerant quantum computing. Recently, quantum error correction has experienced significant progress both in code development and experimental realizations, with neutral atom qubit architecture rapidly establishing itself as a leading platform in the field. Scalable quantum computing will require processing with QEC codes that have low qubit overhead and large error suppression, and while such codes do exist, they involve a degree of non-locality that has yet to be integrated into experimental platforms. In this work, we analyze a family of high-rate Low-Density Parity-Check (LDPC) codes with limited long-range interactions and outline a near-term implementation in neutral atom registers. By means of circuit-level simulations, we find that these codes outperform surface codes in all respects when the two-qubit nearest neighbour gate error probability is below ~ 0.1%. By using multiple laser colors, we show how these codes can be natively integrated in two-dimensional static neutral atom qubit architectures with open boundaries, where the desired long-range connectivity can be targeted via the Rydberg blockade interaction. Quantum error correction codes with low qubit overhead and error suppression capabilities are highly desirable for fault-tolerant quantum computing. Here, the authors introduce a family of high-rate Low Density Parity-Check quantum error correcting codes with moderate long-range connectivity and outline a near-term implementation in static neutral atom registers.
Quantum low-density parity-check codes are promising candidates towards scalable fault-tolerant quantum computation. Among these, bivariate bicycle (BB) codes offer superior encoding rates and large code distance compared to surface codes. However, their requirement on long-range stabilizer measurements poses significant challenges for implementation on realistic hardware with limited connectivity, such as superconducting circuit platforms. In this work, we introduce a novel hardware-software co-design that leverages a programmable communication network architecture to address these limitations. Our approach utilizes a 2D toric network of oscillators as a flexible communication fabric linking qubits at each site. Such architecture significantly reduces the number of long-range couplers required from O(n) to O(n). Dual-rail qubits, along with native gates including Swap-Wait-Swap gates and beamsplitter SWAPs, ensure that long-range two-qubit gates can be executed with high fidelity and low latency. To further enhance performance, our qubit layout and routing algorithm utilize symmetries of the codes and enable maximum parallelism for long-range two-qubit gates, maintaining a low syndrome extraction cycle duration and scalability over the code length. We perform circuit-level simulation with realistic noise modeling based on experimental hardware parameters, observing an logical error rate per logical qubit per cycle of 3.06\% for [[18,4,4]] BB code, 2.6× less than the existing experimental result. These findings provide a practical roadmap and identify key technological advancements needed to achieve low-overhead fault-tolerant quantum computing at scale.
Quantum low-density parity-check (QLDPC) codes with good parameters are promising candidates for low-overhead fault-tolerant quantum computing, but their non-local stabilizers require long-range connectivity and frequent qubit movement, introducing practical challenges. Prior work has studied the networked implementation of topological codes, where each node only holds one or a few qubits of the entire code, and demonstrated competitive performance under practical constraints such as the quality of network-provided entanglement. However, since these codes are already geometrically local, such a networked setting might not be essential. In this work, we propose and study the networked implementation of better QLDPC codes, specifically bivariate bicycle codes due to their similarity to surface codes and the controlled amount of long-range connections in their stabilizers. We begin by recreating networked surface codes in Stim, with one code qubit per node, and provide additional insights into their circuit-level noise performance. We then extend this approach to bipartitions of bivariate bicycle codes, using balanced min-cut partitioning on their combined X-Z Tanner graph to identify optimal qubit splits. For stabilizers spanning nodes, we implement teleported CNOTs and vary the Bell pair fidelity enabling these gates. Through circuit-level noise simulations with BP-OSD decoding, we provide the first insights into networked realizations of these codes and compare their performance with monolithic implementations. We conclude by outlining advantages, limitations, and future directions.