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arXiv:2403.12857

Average circuit eigenvalue sampling on NISQ devices

Emilio Peláez, Victory Omole, Pranav Gokhale, Rich Rines, Kaitlin N. Smith, Michael A. Perlin, Akel Hashim

Published Mar 19, 2024• 0 citations
arXivHTMLPDF

Abstract

Average circuit eigenvalue sampling (ACES) was introduced by Flammia in arXiv:2108.05803 as a protocol to characterize the Pauli error channels of individual gates across the device simultaneously. The original paper posed using ACES to characterize near-term devices as an open problem. This work advances in this direction by presenting a full implementation of ACES for real devices and deploying it to Superstaq arXiv:2309.05157, along with a device-tailored resource estimation obtained through simulations and experiments. Our simulations show that ACES is able to estimate one- and two-qubit non-uniform Pauli error channels to an average eigenvalue absolute error of under $0.003$ and total variation distance of under 0.001 between simulated and reconstructed probability distributions over Pauli errors with $10^5$ shots per circuit using 5 circuits of depth 14. The question of estimating general error channels through twirling techniques in real devices remains open, as it is dependent on a device's native gates, but simulations with the Clifford set show results in agreement with reported hardware data. Experimental results on IBM's Algiers and Osaka devices are presented, where we characterize their error channels as Pauli channels without twirling.

DOI
10.48550/arxiv.2403.12857

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Average circuit eigenvalue sampling (ACES) was introduced by Flammia in arXiv:2108.05803 as a protocol to characterize the Pauli error channels of individual gates across the device simultaneously. The original paper posed using ACES to characterize near-term devices as an open problem. This work advances in this direction by presenting a full implementation of ACES for real devices and deploying it to Superstaq arXiv:2309.05157, along with a device-tailored resource estimation obtained through simulations and experiments. Our simulations show that ACES is able to estimate one- and two-qubit non-uniform Pauli error channels to an average eigenvalue absolute error of under 0.0030.0030.003 and total variation distance of under 0.001 between simulated and reconstructed probability distributions over Pauli errors with 10510^5105 shots per circuit using 5 circuits of depth 14. The question of estimating general error channels through twirling techniques in real devices remains open, as it is dependent on a device's native gates, but simulations with the Clifford set show results in agreement with reported hardware data. Experimental results on IBM's Algiers and Osaka devices are presented, where we characterize their error channels as Pauli channels without twirling.
We introduce ACES, a method for scalable noise metrology of quantum circuits that stands for Averaged Circuit Eigenvalue Sampling. It simultaneously estimates the individual error rates of all the gates in collections of quantum circuits, and can even account for space and time correlations between these gates. ACES strictly generalizes randomized benchmarking (RB), interleaved RB, simultaneous RB, and several other related techniques. However, ACES provides much more information and provably works under strictly weaker assumptions than these techniques. Finally, ACES is extremely scalable: we demonstrate with numerical simulations that it simultaneously and precisely estimates all the Pauli error rates on every gate and measurement in a 100 qubit quantum device using fewer than 20 relatively shallow Clifford circuits and an experimentally feasible number of samples. By learning the detailed gate errors for large quantum devices, ACES opens new possibilities for error mitigation, bespoke quantum error correcting codes and decoders, customized compilers, and more.
Characterizing the performance of noisy quantum circuits is central to the production of prototype quantum computers and can enable improved quantum error correction that exploits noise biases identified in a quantum device. We develop a scalable noise-characterization protocol suited to characterizing the syndrome-extraction circuits of quantum error-correcting codes, a key component of fault-tolerant architectures. Our protocol builds upon averaged circuit eigenvalue sampling (ACES), a framework for noise-characterization experiments that simultaneously estimates the Pauli-error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. By rigorously analyzing the performance of noise-characterization experiments in the ACES framework, we derive a figure of merit for their expected performance, allowing us to optimize their experimental design and improve the precision to which we estimate noise given fixed experimental resources. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise-characterization procedure for the syndrome-extraction circuit of a distance- 25 surface code with over 1000 qubits. Our results indicate that detailed noise-characterization methods are scalable to near-term quantum devices.
Efficient characterization of noise during quantum gate operations is an essential step to building and scaling up a quantum computer. One such protocol is averaged circuit eigenvalue sampling (ACES) which efficiently characterizes a noisy gate set by reconstructing a Pauli noise model for a each gate. Here we utilize the ACES protocol to characterize two coupled superconducting qubits. For accurate reconstruction, we tailor the noise via Pauli twirling and account for measurement errors. We verify the accuracy of the protocol by comparing the predicted gate fidelities to that extracted from conventional benchmarking approaches, such as interleaved randomized benchmarking. Furthermore, we demonstrate the efficacy of ACES in accurately identifying specific noise sources by reconstructing injected phase errors in the two-qubit gates.
Noise is the fundamental challenge to quantum computation. Large-scale quantum computers will overcome this challenge with fault-tolerant architectures that leverage quantum error correction. This thesis introduces and investigates a scalable noise characterisation protocol suited to this key context. First, we introduce this protocol by building upon averaged circuit eigenvalue sampling (ACES), a framework for noise characterisation experiments that simultaneously estimates the Pauli error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise characterisation procedure. Then we demonstrate in circuit-level numerical simulation that this protocol is practically capable of calibrating a fast correlated matching decoder, enabling noise-aware decoding. We find that noise-aware decoding increases the error suppression factor of the code, leading to reductions in the logical error rate that increase exponentially with the code distance. Finally, we present several results obtained from experimentally implementing this protocol. We use the noise characterisation results to design an improved syndrome extraction circuit for a heavy hexagon memory that is adapted to the noise characteristics of the quantum device. The model error of our noise characterisation results suggests that the circuit-level Pauli noise model estimated by ACES can describe the essential features of quantum noise. We also operate a heavy hexagon memory and use noise estimates to predict performance and inform decoding. These results demonstrate that Pauli noise estimates can calibrate decoders to enable noise-aware decoding and inform the co-design of quantum error correcting codes, decoders, fault-tolerant circuits, and quantum devices.
Abstract Quantum noise limits the reliability of noisy intermediate-scale quantum (NISQ) devices. Quantum error mitigation (QEM) provides a near-term path to improved accuracy, with randomized compiling (RC) serving as a key technique for transforming arbitrary gate noise into a stochastic Pauli form. However, its sampling complexity grows exponentially with circuit depth, hindering practical use. We introduce twirling scheduling (TS), which groups gate cycles into configurable units twirled collectively. By incorporating pseudo-twirling for non-Clifford gates, TS reduces the sampling-space dimension, mitigating this exponential scaling. Our theoretical analysis provides rigorous error bounds. Numerical simulations on Quantum Approximate Optimization Algorithm circuits up to 50 layers show that TS reduces estimation error by approximately 62% compared to conventional RC under a very small sampling budget and maintains superior performance when combined with established QEM protocols, including zero-noise extrapolation, Clifford data regression, and virtual distillation. TS thus offers a scalable, practical advance for error-mitigated quantum computation on NISQ hardware.
Fault-tolerant quantum design relies on simulating noisy quantum error correction (QEC) circuits with hundreds to thousands of physical qubits and large circuit depths. High-throughput stabilizer simulators, such as Stim, are the de facto tools for this regime. However, these simulators typically support only Clifford gates and stochastic Pauli noise. As a result, more realistic device noise models-such as coherent control errors and thermal relaxation-are often approximated using Pauli Twirling. This replacement offers speed but can introduce inaccuracies. To address this, we propose QuasiStim for scalable exact QEC simulation of realistic noise, with QuasiFold as a compiler frontend and DeltaFrame as a sampling backend. QuasiFold lowers sampling overhead by merging equivalent non-Pauli sites in the quantum circuit. DeltaFrame samples the resulting stabilizer trajectories by reusing precomputed predicted references instead of resimulating the full tableau for each shot. QuasiFold can reduce the number of shots by over 100×100\times100× on bivariate-bicycle (BB) codes. Compared to a per-shot tableau simulator, DeltaFrame is 166×166\times166×--1331×1331\times1331× faster on rotated surface-code memory under coherent RZR_ZRZ​ noise as ddd grows from 5 to 35. QuasiStim also makes the PTA bias measurable: the gap is non-negligible and varies with noise strength, decoder, and circuit schedule. QuasiStim will be open-sourced upon publication at https://github.com/isaachyw/QuasiStim