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arXiv:2108.05803 · Leibniz international proceedings in informatics

Averaged Circuit Eigenvalue Sampling

Steven T. Flammia

Published Aug 12, 2021• 17 citations
arXivHTMLPDF

Abstract

We introduce ACES, a method for scalable noise metrology of quantum circuits that stands for Averaged Circuit Eigenvalue Sampling. It simultaneously estimates the individual error rates of all the gates in collections of quantum circuits, and can even account for space and time correlations between these gates. ACES strictly generalizes randomized benchmarking (RB), interleaved RB, simultaneous RB, and several other related techniques. However, ACES provides much more information and provably works under strictly weaker assumptions than these techniques. Finally, ACES is extremely scalable: we demonstrate with numerical simulations that it simultaneously and precisely estimates all the Pauli error rates on every gate and measurement in a 100 qubit quantum device using fewer than 20 relatively shallow Clifford circuits and an experimentally feasible number of samples. By learning the detailed gate errors for large quantum devices, ACES opens new possibilities for error mitigation, bespoke quantum error correcting codes and decoders, customized compilers, and more.

DOI
10.4230/lipics.tqc.2022.4

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We introduce ACES, a method for scalable noise metrology of quantum circuits that stands for Averaged Circuit Eigenvalue Sampling. It simultaneously estimates the individual error rates of all the gates in collections of quantum circuits, and can even account for space and time correlations between these gates. ACES strictly generalizes randomized benchmarking (RB), interleaved RB, simultaneous RB, and several other related techniques. However, ACES provides much more information and provably works under strictly weaker assumptions than these techniques. Finally, ACES is extremely scalable: we demonstrate with numerical simulations that it simultaneously and precisely estimates all the Pauli error rates on every gate and measurement in a 100 qubit quantum device using fewer than 20 relatively shallow Clifford circuits and an experimentally feasible number of samples. By learning the detailed gate errors for large quantum devices, ACES opens new possibilities for error mitigation, bespoke quantum error correcting codes and decoders, customized compilers, and more.
Characterizing the performance of noisy quantum circuits is central to the production of prototype quantum computers and can enable improved quantum error correction that exploits noise biases identified in a quantum device. We develop a scalable noise-characterization protocol suited to characterizing the syndrome-extraction circuits of quantum error-correcting codes, a key component of fault-tolerant architectures. Our protocol builds upon averaged circuit eigenvalue sampling (ACES), a framework for noise-characterization experiments that simultaneously estimates the Pauli-error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. By rigorously analyzing the performance of noise-characterization experiments in the ACES framework, we derive a figure of merit for their expected performance, allowing us to optimize their experimental design and improve the precision to which we estimate noise given fixed experimental resources. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise-characterization procedure for the syndrome-extraction circuit of a distance- 25 surface code with over 1000 qubits. Our results indicate that detailed noise-characterization methods are scalable to near-term quantum devices.
Efficient characterization of noise during quantum gate operations is an essential step to building and scaling up a quantum computer. One such protocol is averaged circuit eigenvalue sampling (ACES) which efficiently characterizes a noisy gate set by reconstructing a Pauli noise model for a each gate. Here we utilize the ACES protocol to characterize two coupled superconducting qubits. For accurate reconstruction, we tailor the noise via Pauli twirling and account for measurement errors. We verify the accuracy of the protocol by comparing the predicted gate fidelities to that extracted from conventional benchmarking approaches, such as interleaved randomized benchmarking. Furthermore, we demonstrate the efficacy of ACES in accurately identifying specific noise sources by reconstructing injected phase errors in the two-qubit gates.
Noise is the fundamental challenge to quantum computation. Large-scale quantum computers will overcome this challenge with fault-tolerant architectures that leverage quantum error correction. This thesis introduces and investigates a scalable noise characterisation protocol suited to this key context. First, we introduce this protocol by building upon averaged circuit eigenvalue sampling (ACES), a framework for noise characterisation experiments that simultaneously estimates the Pauli error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise characterisation procedure. Then we demonstrate in circuit-level numerical simulation that this protocol is practically capable of calibrating a fast correlated matching decoder, enabling noise-aware decoding. We find that noise-aware decoding increases the error suppression factor of the code, leading to reductions in the logical error rate that increase exponentially with the code distance. Finally, we present several results obtained from experimentally implementing this protocol. We use the noise characterisation results to design an improved syndrome extraction circuit for a heavy hexagon memory that is adapted to the noise characteristics of the quantum device. The model error of our noise characterisation results suggests that the circuit-level Pauli noise model estimated by ACES can describe the essential features of quantum noise. We also operate a heavy hexagon memory and use noise estimates to predict performance and inform decoding. These results demonstrate that Pauli noise estimates can calibrate decoders to enable noise-aware decoding and inform the co-design of quantum error correcting codes, decoders, fault-tolerant circuits, and quantum devices.
Average circuit eigenvalue sampling (ACES) was introduced by Flammia in arXiv:2108.05803 as a protocol to characterize the Pauli error channels of individual gates across the device simultaneously. The original paper posed using ACES to characterize near-term devices as an open problem. This work advances in this direction by presenting a full implementation of ACES for real devices and deploying it to Superstaq arXiv:2309.05157, along with a device-tailored resource estimation obtained through simulations and experiments. Our simulations show that ACES is able to estimate one- and two-qubit non-uniform Pauli error channels to an average eigenvalue absolute error of under 0.0030.0030.003 and total variation distance of under 0.001 between simulated and reconstructed probability distributions over Pauli errors with 10510^5105 shots per circuit using 5 circuits of depth 14. The question of estimating general error channels through twirling techniques in real devices remains open, as it is dependent on a device's native gates, but simulations with the Clifford set show results in agreement with reported hardware data. Experimental results on IBM's Algiers and Osaka devices are presented, where we characterize their error channels as Pauli channels without twirling.
Benchmarking methods that can be adapted to multiqubit systems are essential for assessing the overall or "holistic" performance of nascent quantum processors. The current industry standard is Clifford randomized benchmarking (RB), which measures a single error rate that quantifies overall performance. But, scaling Clifford RB to many qubits is surprisingly hard. It has only been performed on one, two, and three qubits as of this writing. This reflects a fundamental inefficiency in Clifford RB: the n-qubit Clifford gates at its core have to be compiled into large circuits over the one- and two-qubit gates native to a device. As n grows, the quality of these Clifford gates quickly degrades, making Clifford RB impractical at relatively low n. In this Letter, we propose a direct RB protocol that mostly avoids compiling. Instead, it uses random circuits over the native gates in a device, which are seeded by an initial layer of Clifford-like randomization. We demonstrate this protocol experimentally on two to five qubits using the publicly available ibmqx5. We believe this to be the greatest number of qubits holistically benchmarked, and this was achieved on a freely available device without any special tuning up. Our protocol retains the simplicity and convenient properties of Clifford RB: it estimates an error rate from an exponential decay. But, it can be extended to processors with more qubits-we present simulations on 10+ qubits-and it reports a more directly informative and flexible error rate than the one reported by Clifford RB. We show how to use this flexibility to measure separate error rates for distinct sets of gates, and we use this method to estimate the average error rate of a set of cnot gates.
Accurate benchmarking of quantum gates is crucial for understanding and enhancing the performance of quantum hardware. A standard method for this is interleaved benchmarking, a technique which estimates the error on an interleaved target gate by comparing cumulative error rates of randomized sequences implemented with the interleaved gate and without it. In this work, we show both numerically and experimentally that the standard approach of interleaved randomized benchmarking (IRB), which uses the multi-qubit Clifford group for randomization, can produce highly inaccurate and even physically impossible estimates for the error on the interleaved gate in the presence of coherent errors. Fortunately we also show that interleaved benchmarking performed with cycle benchmarking, which randomizes with single qubit Pauli gates, provides dramatically reduced systematic uncertainty relative to standard IRB, and further provides as host of additional benefits including data reusability. We support our conclusions with a theoretical framework for bounding systematic errors, extensive numerical results comparing a range of interleaved protocols under fixed resource costs, and experimental demonstrations on three quantum computing platforms.