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arXiv:2403.00363

SFQ counter-based precomputation for large-scale cryogenic VQE machines

Yosuke Ueno, Imamura, Satoshi, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

Published Mar 1, 2024• 2 citations
arXivHTMLPDF

Abstract

The variational quantum eigensolver (VQE) is a promising candidate that brings practical benefits from quantum computing. However, the required bandwidth in/out of a cryostat is a limiting factor to scale cryogenic quantum computers. We propose a tailored counter-based module with single flux quantum circuits in 4-K stage which precomputes a part of VQE calculation and reduces the amount of inter-temperature communication. The evaluation shows that our system reduces the required bandwidth by 97%, and with this drastic reduction, total power consumption is reduced by 93% in the case where 277 VQE programs are executed in parallel on a 10000-qubit machine.

DOI
10.48550/arxiv.2403.00363

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The variational quantum eigensolver (VQE) is a promising candidate that brings practical benefits from quantum computing. However, the required bandwidth in/out of a cryostat is a limiting factor to scale cryogenic quantum computers. We propose a tailored counter-based module with single flux quantum circuits in 4-K stage which precomputes a part of VQE calculation and reduces the amount of inter-temperature communication. The evaluation shows that our system reduces the required bandwidth by 97%, and with this drastic reduction, total power consumption is reduced by 93% in the case where 277 VQE programs are executed in parallel on a 10000-qubit machine.
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The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.
The number of bits in quantum computers needs to be increased since large problems must be solved to achieve quantum acceleration. Superconducting qubits are the most advanced qubit devices currently available. A method has been proposed to place a quantum-classical interface on a 4 K stage to ensure scalability. The practical implications of a simple counter circuit in the interface and its role in processing the qubit read results have been demonstrated. A method is needed for configuring a counter circuit with low power consumption to improve scalability. In this paper, we design a novel counter circuit using the Half-Flux Quantum (HFQ) technology. This technology operates in cryogenic environments and has lower power consumption than the Single-Flux Quantum (SFQ) tech-nology. In addition, we conducted a comparative evaluation of circuits dedicated to the NISQ algorithm using SFQ and equivalent circuits implemented using HFQ. Assuming the same power consumption technology applicable to SFQ can be applied to HFQ, we found that the proposed HFQ-based counter circuit can reduce the power consumption by up to 97%.
As quantum computing processors increase in size, there is growing interest in developing cryogenic electronics to overcome significant challenges to system scaling. Single flux-quantum (SFQ) circuits offer a promising alternative to remote, bulky, and power-hungry room temperature electronics. To meet the need for digital qubit control, readout, and co-processing, SFQ circuits must be adapted to operate at millikelvin temperatures near quantum processors. SEEQC's SFQuClass digital quantum management approach proximally places energy-efficient SFQ (ERSFQ) circuits and qubits in a multi-chip module. This enables extremely low power dissipation, compatible with a typical dilution cryostat's limited cooling power, while maintaining high processing speed and low error rates. We report on systematic testing from 4 K to 10 mK of a comprehensive set of ERSFQ cells, as well as more complex circuits such as programmable counters and demultiplexers used in digital qubit control. We compare the operating margins and error rates of these circuits and find that, at millikelvin, bias margins decrease and the center of the margins (i.e., the optimal bias current value) increases by ~15%, compared to 4.2 K. The margins can be restored by thermal annealing by reducing Josephson junction (JJ) critical current Ic. To provide guidance for how circuit parameters vary from 4.2 K to millikelvin, relevant analog process control monitors (PCMs) were tested in the temperature range of interest. The measured JJ critical current (of the PCM JJ arrays) increases by ~15% when decreasing temperature from 4.2 K to millikelvin, in good agreement with both theory and the empirically measured change in the center of bias margins for the tested digital circuits.
The digital circuits in a superconducting quantum computer must be cooled to cryogenic temperatures in a dilution refrigerator for control and information readout of the qubit information. Because the dilution refrigerator's heat capacity is limited, extremely low-power digital circuits are required. Single-flux-quantum (SFQ) circuits and Josephson photomultipliers (JPMs) are expected to serve as control and readout circuits for superconducting quantum computers. These circuits generate minimal heat, but further reductions in power consumption are required to make it possible to build larger, more scalable faulttolerant quantum computers (FTQC). In this paper, we propose a low-power and reliable peripheral circuit for JPM-based qubit readout utilizing an SFQ counter circuit. The counter performs majority voting across repeated readouts, significantly improving the reliability of the JPM readout process. Additionally, we quantitatively evaluate switching errors in SFQ circuits using Josephson junctions with low-critical current values. By integrating these circuit techniques and simulation results, we find that the proposed approach achieves a 90% reduction in power consumption while effectively suppressing the increase in readout error.
Readout and control of qubits are limiting factors in scaling quantum computers. An ideal solution is to integrate energy-efficient cryogenic circuits close to the qubits to perform control and pre-processing tasks. With orders of magnitude lower power consumption and hence lower noise, Single Flux Quantum (SFQ) and Adiabatic Quantum Flux Parametron (AQFP) superconductor logic families can reach ultimate performance at cryogenic temperatures. We have created a superconductor-based on-chip function generator to control qubits. The generated signal is modulated up to tens of GHz based on the external input waveform applied to the superconductor mixer stage. This circuit works at 4.2K. A radiofrequency (RF) matching circuit transmits the signal to the ~mK stage after digital amplification and noise reduction.