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arXiv:2312.16114

Quantum Fourier Transformation Circuits Compilation

Yuwei Jin, Xiangyu Gao, Minghao Guo, Chen, Henry, Fei Hua, Zhang, Chi, Eddy Z. Zhang

Published Dec 17, 2023• 3 citations
arXivHTMLPDF

Abstract

In this research paper, our primary focus revolves around the domain-specific hardware mapping strategy tailored for Quantum Fourier Transformation (QFT) circuits. While previous approaches have heavily relied on SAT solvers or heuristic methods to generate hardware-compatible QFT circuits by inserting SWAP gates to realign logical qubits with physical qubits at various stages, they encountered significant challenges. These challenges include extended compilation times due to the expansive search space for SAT solvers and suboptimal outcomes in terms of the number of cycles required to execute all gate operations efficiently. In our study, we adopt a novel approach that combines technical intuition, often referred to as "educated guesses," and sophisticated program synthesis tools. Our objective is to uncover QFT mapping solutions that leverage concepts such as affine loops and modular functions. The groundbreaking outcome of our research is the introduction of the first set of linear-depth transformed QFT circuits designed for Google Sycamore, IBM heavy-hex, and the conventional 2-dimensional (2D) grid configurations, accommodating an arbitrary number of qubits denoted as 'N'. Additionally, we have conducted comprehensive analyses to verify the correctness of these solutions and to develop strategies for handling potential faults within them.

DOI
10.48550/arxiv.2312.16114

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In this research paper, our primary focus revolves around the domain-specific hardware mapping strategy tailored for Quantum Fourier Transformation (QFT) circuits. While previous approaches have heavily relied on SAT solvers or heuristic methods to generate hardware-compatible QFT circuits by inserting SWAP gates to realign logical qubits with physical qubits at various stages, they encountered significant challenges. These challenges include extended compilation times due to the expansive search space for SAT solvers and suboptimal outcomes in terms of the number of cycles required to execute all gate operations efficiently. In our study, we adopt a novel approach that combines technical intuition, often referred to as "educated guesses," and sophisticated program synthesis tools. Our objective is to uncover QFT mapping solutions that leverage concepts such as affine loops and modular functions. The groundbreaking outcome of our research is the introduction of the first set of linear-depth transformed QFT circuits designed for Google Sycamore, IBM heavy-hex, and the conventional 2-dimensional (2D) grid configurations, accommodating an arbitrary number of qubits denoted as 'N'. Additionally, we have conducted comprehensive analyses to verify the correctness of these solutions and to develop strategies for handling potential faults within them.
Rapid development in quantum computing leads to the appearance of several quantum applications. Quantum Fourier Transformation (QFT) sits at the heart of many of these applications. Existing work leverages SAT solver or heuristics to generate a hardware-compliant circuit for QFT by inserting SWAP gates to remap logical qubits to physical qubits. However, they might face problems such as long compilation time due to the huge search space for SAT solver or suboptimal outcome in terms of the number of cycles to finish all gate operations. In this paper, we propose a domain-specific hardware mapping approach for QFT. We unify our insight of relaxed ordering and unit exploration in QFT to search for a qubit mapping solution with the help of program synthesis tools. Our method is the first one that guarantees linear-depth QFT circuits for Google Sycamore, IBM heavy-hex, and the lattice surgery, with respect to the number of qubits. Compared with state-of-the-art approaches, our method can save up to 53% in SWAP gate and 92% in depth.
Compiling a given quantum algorithm into a target hardware architecture is a challenging optimization problem. The compiler must take into consideration the coupling graph of physical qubits and the gate operation dependencies. The existing noise in hardware architectures requires the compilation to use as few running cycles as possible. Existing approaches include using SAT solver or heuristics to complete the mapping but these may cause the issue of either long compilation time (e.g., timeout after hours) or suboptimal compilation results in terms of running cycles (e.g., exponentially increasing number of total cycles). In this paper, we propose an efficient mapping approach for Quantum Fourier Transformation (QFT) circuits over the existing IBM heavy-hex architecture. Such proposal first of all turns the architecture into a structure consisting of a straight line with dangling qubits, and then do the mapping over this generated structure recursively. The calculation shows that there is a linear depth upper bound for the time complexity of these structures and for a special case where there is 1 dangling qubit in every 5 qubits, the time complexity is 5N+O(1). All these results are better than state of the art methods.
Rapid progress in the physical implementation of quantum computers gave birth to multiple recent quantum machines implemented with superconducting technology. In these NISQ machines, each qubit is physically connected to a bounded number of neighbors. This limitation prevents most quantum programs from being directly executed on quantum devices. A compiler is required for converting a quantum program to a hardware-compliant circuit, in particular, making each two-qubit gate executable by mapping the two logical qubits to two physical qubits with a link between them. To solve this problem, existing studies focus on inserting SWAP gates to dynamically remap logical qubits to physical qubits. However, most of the schemes lack the consideration of time-optimality of generated quantum circuits, or are achieving time-optimality with certain constraints. In this work, we propose a theoretically time-optimal SWAP insertion scheme for the qubit mapping problem. Our model can also be extended to practical heuristic algorithms. We present exact analysis results by using our model for quantum programs with recurring execution patterns. We have for the first time discovered an optimal qubit mapping pattern for quantum fourier transformation (QFT) on 2D nearest neighbor architecture. We also present a scalable extension of our theoretical model that can be used to solve qubit mapping for large quantum circuits.
In the era of noisy intermediate-scale quantum (NISQ) computing, the limited connectivity between qubits is one of the common physical limitations faced by current quantum computing devices. Quantum circuit mapping methods transform quantum circuits into equivalent circuits that satisfy physical connectivity constraints by remapping logical qubits, making them executable. The optimization problem of quantum circuit mapping has NP-hard computational complexity, and existing heuristic mapping algorithms still have significant potential for optimization in terms of the number of quantum gates generated. To reduce the number of SWAP gates inserted during mapping, the solution space of the mapping problem is represented as a tree structure, and the mapping process is equivalent to traversing this tree structure. To effectively and efficiently complete the search process, a beam search framework (BSF) is proposed for solving quantum circuit mapping. By iteratively selecting, expanding, and making decisions, high-quality target circuits are generated. Experimental results show that this method can significantly reduce the number of inserted SWAP gates on medium to large circuits, achieving an average reduction of 44% compared to baseline methods, and is applicable to circuits of various sizes and complexities.
Quantum circuit compilation is a multi-stage process that translates a high-level quantum circuit representation into a sequence of quantum gates that can be directly executed by a quantum machine. One of the core steps in quantum compilation is mapping, a procedure that transforms a quantum circuit into a semantically equivalent circuit while inserting additional gates to comply with the architectural constraints of the underlying quantum hardware. Current mapping techniques exhibit significant performance degradation—in terms of circuit depth and gate count—when applied to large-scale circuits containing hundreds of thousands of gates or more. In this work, we propose a novel methodology to enhance quantum compiler capabilities by adapting general principles from classical Electronic Design Automation. We model the quantum hardware as being composed of standard cells, onto which portions of the circuit are mapped using a floorplanning-based technique. This contrasts with current state-of-the-art solutions, which perform mapping at the gate level without considering any form of hierarchical abstraction. We use the ChaCha20 stream cipher as a running example to validate and explain our strategy. We evaluate our methodology using two well-known, industrial-grade quantum compilers: IBM Qiskit and Quantinuum TKET. Compared to these compilers, our approach achieves an average circuit depth reduction of 59.78% and 68.85%, respectively, and a gate count reduction of 4.07 % and 6.20 %, respectively. These results are obtained across a large set of randomly generated quantum circuit descriptions in the range of millions of gates, with varying input and output connectivity for each block in the circuit.
Noisy Intermediate-Scale Quantum (NISQ) computers impose severe architectural constraints that prevent direct execution of logical quantum circuits. As a result, quantum circuit mapping—transforming ideal circuits into hardware-compatible forms—has become a critical task in quantum software toolchains. This paper presents a comparative study of key mapping techniques, focusing on circuit depth, SWAP gate overhead, and fidelity awareness. Through a case analysis on a 5-qubit Quantum Fourier Transform (QFT) circuit, we demonstrate the performance trade-offs of several prominent mapping strategies, including naive greedy routing, Qiskit’s SABRE, and CQC’s t|ket>. Our findings reveal that mapping technique selection has a profound impact on circuit quality and feasibility on real NISQ hardware.