Reaching fault-tolerant quantum computation relies on the successful implementation of non-Clifford circuits with quantum error correction (QEC). In QEC, quantum gates and measurements encode quantum information into an error-protected Hilbert space, while classical processing decodes the measurements into logical errors. QEC non-Clifford gates pose the greatest computation challenge from the classical controller's perspective, as they require mid-circuit decoding-dependent feed-forward—modifying the physical gate sequence based on the decoding outcome of previous measurements within the same circuit. In this work, we introduce the first benchmarks to holistically evaluate the capability of a combined controller–decoder system to run non-Clifford QEC circuits. We show that executing an error-corrected non-Clifford circuit, comprised of numerous non-Clifford gates, strictly hinges upon the classical controller–decoder system. Particularly, its ability to perform decoding-based feed-forward with low latency, defined as the time between the last measurement required for decoding and the dependent mid-circuit quantum operation. We analyze how the system's latency dictates the circuit's operational regime: latency divergence, classical-controller-limited runtime, or quantum-operation-limited runtime. Based on this understanding, we introduce latency-based benchmarks to set a standard for developing QEC control systems as the essential components of fault-tolerant quantum computation.
Reaching fault-tolerant quantum computation relies on the successful implementation of non-Clifford circuits with quantum error correction (QEC). In QEC, quantum gates and measurements encode quantum information into an error-protected Hilbert space, while classical processing decodes the measurements into logical errors. QEC non-Clifford gates pose the greatest computation challenge from the classical controller's perspective, as they require mid-circuit decoding-dependent feed-forward—modifying the physical gate sequence based on the decoding outcome of previous measurements within the same circuit. In this work, we introduce the first benchmarks to holistically evaluate the capability of a combined controller–decoder system to run non-Clifford QEC circuits. We show that executing an error-corrected non-Clifford circuit, comprised of numerous non-Clifford gates, strictly hinges upon the classical controller–decoder system. Particularly, its ability to perform decoding-based feed-forward with low latency, defined as the time between the last measurement required for decoding and the dependent mid-circuit quantum operation. We analyze how the system's latency dictates the circuit's operational regime: latency divergence, classical-controller-limited runtime, or quantum-operation-limited runtime. Based on this understanding, we introduce latency-based benchmarks to set a standard for developing QEC control systems as the essential components of fault-tolerant quantum computation.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Quantum Error Correction (QEC) is regarded as the most promising path to quantum advantage. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC: a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable by distributing decoding data into several decoders while ensuring fast communication between decoders and with the controller. By extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance in the scale of 0.1% physical error rates and 1000 qubits, are sufficient for a successful circuit execution. Overall, the requirements outlined here set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits.
Abstract The ability to perform quantum error correction (QEC) and robust gate operations on encoded qubits opens the door to demonstrations of quantum algorithms. Contemporary QEC schemes typically require mid-circuit measurements with feed-forward control, which are challenging for qubit control, often slow, and susceptible to relatively high error rates. In this work, we propose and experimentally demonstrate a universal toolbox of fault-tolerant logical operations without mid-circuit measurements on a trapped-ion quantum processor. We present modular logical state teleportation between two four-qubit error-detecting codes without measurements during algorithm execution. Moreover, we realize a fault-tolerant universal gate set on an eight-qubit error-detecting code hosting three logical qubits, based on state injection, which can be executed by coherent gate operations only. We apply this toolbox to experimentally realize Grover's quantum search algorithm fault-tolerantly on three logical qubits encoded in eight physical qubits, with the implementation displaying clear identification of the desired solution states. Our work demonstrates the practical feasibility and provides first steps into the largely unexplored direction of measurement-free quantum computation.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Quantum error correction (QEC) enables reliable computation on noisy hardware by encoding logical information across many physical qubits and periodically measuring parities to detect errors. A decoder is the classical algorithm that uses these measurements to infer which error most likely occurred, so that the system can correct it. The decoder's accuracy-how rarely it makes the wrong guess-directly determines the scale of quantum computation that can be reliably executed. With a wealth of competing decoding algorithms, a QEC system designer needs reliable methods to evaluate them. Today, the dominant approach is to evaluate decoders using Monte Carlo simulation. However, simulation has several drawbacks such as requiring many samples to produce low variance estimates.
In this work, we develop a new systematic analysis for evaluating decoders. We introduce a novel formal semantics of a core language for QEC programs that captures the de facto standard Stim circuit format, providing a principled theoretical foundation for the emerging space of fault-tolerant quantum systems design. Given a QEC program and a decoder, our verifier can quantify both the decoder accuracy and the decoder robustness to drift in physical error rate. Our approach has two key components: (i) a structured search over the space of possible errors; and (ii) a constrained polynomial optimization kernel. A thorough empirical evaluation of our approach suggests that it can outperform simulation, especially in low error rate regimes, and that it can be deployed to quantify decoder robustness over an interval of physical error rates.
The ability to perform quantum error correction (QEC) and robust gate operations on encoded qubits opens the door to demonstrations of quantum algorithms. Contemporary QEC schemes typically require mid-circuit measurements with feed-forward control, which are challenging for qubit control, often slow, and susceptible to relatively high error rates. In this work, we propose and experimentally demonstrate a universal toolbox of fault-tolerant logical operations without mid-circuit measurements on a trapped-ion quantum processor. We present modular logical state teleportation between two four-qubit error-detecting codes without measurements during algorithm execution. Moreover, we realize a fault-tolerant universal gate set on an eight-qubit error-detecting code hosting three logical qubits, based on state injection, which can be executed by coherent gate operations only. We apply this toolbox to experimentally realize Grover's quantum search algorithm fault-tolerantly on three logical qubits encoded in eight physical qubits, with the implementation displaying clear identification of the desired solution states. Our work demonstrates the practical feasibility and provides first steps into the largely unexplored direction of measurement-free quantum computation.